EP0032728B1 - Method of mounting a semiconductor device in a housing - Google Patents

Method of mounting a semiconductor device in a housing Download PDF

Info

Publication number
EP0032728B1
EP0032728B1 EP81100276A EP81100276A EP0032728B1 EP 0032728 B1 EP0032728 B1 EP 0032728B1 EP 81100276 A EP81100276 A EP 81100276A EP 81100276 A EP81100276 A EP 81100276A EP 0032728 B1 EP0032728 B1 EP 0032728B1
Authority
EP
European Patent Office
Prior art keywords
adhesive
silver
semiconductor device
layer
housing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP81100276A
Other languages
German (de)
French (fr)
Other versions
EP0032728A3 (en
EP0032728A2 (en
Inventor
Klaus Dieter Exner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=6092314&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP0032728(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0032728A2 publication Critical patent/EP0032728A2/en
Publication of EP0032728A3 publication Critical patent/EP0032728A3/en
Application granted granted Critical
Publication of EP0032728B1 publication Critical patent/EP0032728B1/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • a common method for installing a semiconductor device in a housing is that the underside of the semiconductor body of the semiconductor device is fastened to a metallic housing part serving as a base by means of a metal layer as solder.
  • a cheaper option provides instead of using a metallic intermediate layer, the use of an adhesive consisting of a suitable organic material, which then, for. B. is brought to hardening using an appropriate temperature treatment. Both options can also be used for chip assembly of integrated semiconductor circuits based on monocrystalline silicon and not only for the installation of single semiconductors.
  • US-PS 2774747 the possibility is given to permanently connect the semiconductor device to be installed using an organic adhesive mixed with silver particles to a metallic base, the cement which forms as a result of the curing of the adhesive simultaneously forming an electrically conductive connection between the semiconductor device and the die Semiconductor device forms electrically contacting base.
  • US Pat. No. 3,896,544 describes a semiconductor device which is accommodated in a housing and in which an intermediate layer of elastic silicone rubber, which contains silver particles, is located between the semiconductor arrangement and the metallic housing base. The semiconductor body is pressed against the intermediate layer and the housing base with the aid of a spring.
  • such a type of assembly is not favorable for the installation of integrated circuits.
  • the present invention now relates to a method for installing a semiconductor device, in particular a monolithically integrated semiconductor circuit, in a housing in which the semiconductor body made of silicon of the semiconductor device remains on its underside using an adhesive mixed with silver particles and consisting of organic insulating material a housing part serving as a base and at the same time as a heat sink is connected.
  • the method should also be suitable for the installation of integrated circuits.
  • the underside of the semiconductor body is first covered with a chrome layer and this chrome layer is immediately covered with a silver layer.
  • the thermal resistance R th of a semiconductor system mounted according to the invention is not greater than if it were attached to the metallic base by soldering or alloying.
  • endurance tests have shown that the low heat transfer resistance obtained as a result of the method according to the invention is not destroyed even by long-term alternating loads.
  • Electrodes for semiconductor devices are known from US Pat. No. 3,942,244, the electrodes consisting of a plurality of metal layers applied one above the other. It forms the adjacent to the semiconductor and z. B. consisting of aluminum metal layer with the semiconductor material is an alloy layer.
  • the outer layer of the electrodes can e.g. B. consist of silver.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

Ein übliches Verfahren zum Einbau einer Halbleitervorrichtung in ein Gehäuse besteht darin, daß man die Unterseite des Halbleiterkörpers der Halbleitervorrichtung unter Vermittlung einer Metallschicht als Lot auf einem als Unterlage dienenden metallischen Gehäuseteil befestigt. Eine billigere Möglichkeit sieht anstelle der Verwendung einer metallischen Zwischenschicht die Verwendung eines aus geeignetem organischen Material bestehenden Klebers vor, der dann, z. B. unter Verwendung einer entsprechenden Temperaturbehandlung, zum Aushärten gebracht wird. Beide Möglichkeiten lassen sich auch für die Chip-Montage von aus der Basis von monokristallinem Silicium hergestellten integrierten Halbleiterschaltungen und nicht nur für den Einbau von Einzelhalbleitern einsetzen.A common method for installing a semiconductor device in a housing is that the underside of the semiconductor body of the semiconductor device is fastened to a metallic housing part serving as a base by means of a metal layer as solder. A cheaper option provides instead of using a metallic intermediate layer, the use of an adhesive consisting of a suitable organic material, which then, for. B. is brought to hardening using an appropriate temperature treatment. Both options can also be used for chip assembly of integrated semiconductor circuits based on monocrystalline silicon and not only for the installation of single semiconductors.

In der US-PS 2774747 ist die Möglichkeit angegeben, die einzubauende Halbleitervorrichtung unter Verwendung eines mit Silberpartikeln versetzten organischen Klebers mit einer metallischen Unterlage bleibend zu verbinden, wobei der sich infolge Aushärtung des Klebers bildende Zement zugleich eine elektrisch leitende Verbindung zwischen der Halbleitervorrichtung und der die Halbleitervorrichtung elektrisch kontaktierenden Unterlage bildet. In der US-PS 3896544 ist eine in einem Gehäuse untergebrachte Halbleitervorrichtung beschrieben, bei der sich zwischen der Halbleiteranordnung und dem metallischen Gehäuseboden eine Zwischenlage aus elastischem Silicongummi befindet, der Silberpartikeln enthält. Mit Hilfe einer Feder wird der Halbleiterkörper gegen die Zwischenlage und den Gehäuseboden gedrückt. Eine solche Art der Montage ist jedoch für den Einbau von integrierten Schaltungen nicht günstig.In US-PS 2774747 the possibility is given to permanently connect the semiconductor device to be installed using an organic adhesive mixed with silver particles to a metallic base, the cement which forms as a result of the curing of the adhesive simultaneously forming an electrically conductive connection between the semiconductor device and the die Semiconductor device forms electrically contacting base. US Pat. No. 3,896,544 describes a semiconductor device which is accommodated in a housing and in which an intermediate layer of elastic silicone rubber, which contains silver particles, is located between the semiconductor arrangement and the metallic housing base. The semiconductor body is pressed against the intermediate layer and the housing base with the aid of a spring. However, such a type of assembly is not favorable for the installation of integrated circuits.

Die vorliegende Erfindung befaßt sich nun mit einem Verfahren zum Einbau einer Halbleitervorrichtung, insbesondere einer monolithisch integrierten Halbleiterschaltung, in ein Gehäuse, bei dem der aus Silicium bestehende Halbleiterkörper der Halbleitervorrichtung unter Verwendung eines mit Silberpartikeln versetzten und aus organischem Isoliermaterial bestehenden Klebers an seiner Unterseite bleibend mit einem als Unterlage und zugleich als Wärmesenke dienenden Gehäuseteil verbunden wird.The present invention now relates to a method for installing a semiconductor device, in particular a monolithically integrated semiconductor circuit, in a housing in which the semiconductor body made of silicon of the semiconductor device remains on its underside using an adhesive mixed with silver particles and consisting of organic insulating material a housing part serving as a base and at the same time as a heat sink is connected.

Es ist nun Aufgabe der Erfindung, ein solches Verfahren ohne größeren technischen Aufwand so auszugestalten, daß die Ableitung der beim Betrieb in der eingebauten Halbleitervorrichtung entstehenden Wärme in erheblichem Maße verbessert wird. Außerdem soll das Verfahren für den Einbau von integrierten Schaltungen geeignet sein.It is an object of the invention to design such a method without major technical effort in such a way that the dissipation of the heat generated during operation in the built-in semiconductor device is considerably improved. The method should also be suitable for the installation of integrated circuits.

Erfindungsgemäß ist hierzu vorgesehen, daß vor dem Aufbringen des Klebers die Unterseite des Halbleiterkörpers zunächst mit einer Chromschicht und diese Chromschicht unmittelbar darauf mit einer Silberschicht bedeckt wird.For this purpose, it is provided according to the invention that, before the adhesive is applied, the underside of the semiconductor body is first covered with a chrome layer and this chrome layer is immediately covered with a silver layer.

Der Wärmewiderstand Rth eines entsprechend der Erfindung montierten Halbleitersystems ist nicht größer, als wenn es durch Auflöten oder Auflegieren auf der metallischen Unterlage befestigt wäre. Außerdem haben Dauerversuche gezeigt, daß der aufgrund des erfindungsgemäßen Verfahrens erhaltene niedrige Wärmeübergangswiderstand auch durch langdauernde Wechselbelastungen nicht zerstört wird.The thermal resistance R th of a semiconductor system mounted according to the invention is not greater than if it were attached to the metallic base by soldering or alloying. In addition, endurance tests have shown that the low heat transfer resistance obtained as a result of the method according to the invention is not destroyed even by long-term alternating loads.

Die praktische Durchführung der Erfindung geschieht bevorzugt in folgender Weise :

  • 1. Zunächst wird der aus monokristallinem Silicium bestehende scheibenförmige Halbleiterkörper der zu montierenden Halbleitervorrichtung an der mit der Unterlage zu verbindenden Unterseite durch Schleifen soweit abgetragen, daß eine Gesamtstärke von etwa 180 JLm verbleibt.
  • 2. In einer Bedampfungsanlage wird die Rückseite des scheibenförmigen Halbeiterkörpers bei ca. 300°C mit einer 0,1 JLm starken Chromschicht versehen.
  • 3. Unmittelbar darauf (das heißt, ohne die Bedampfungsanlage zu öffnen) wird auf die Chromschicht eine ca. 1 JLm dicke Silberschicht aufgedampft. Zu bemerken ist dabei, daß man auch mit dünneren Silberschichten, z. B. einer 0,5 JLm starken Silberschicht, noch ausreichend gute Ergebnisse erhält.
  • 4. Die dann aus der Bedampfungsanlage herausgenommene Halbleitervorrichtung wird dann mittels des silberhaltigen Klebers auf dem als Unterlage vorgesehenen und aus wärmeleitendem Material bestehenden Gehäuseteil, insbesondere einer metallischen Gehäuse-Grundplatte, befestigt. Als Kleber ist insbesondere ein Silicon-Kleber (z. B. Z-Kleber) geeignet, der mit dem erforderlichen Gehalt an Silberpartikeln versehen und vor der Anwendung mit ca. 10 % eines geeigneten Lösungsmittels verdünnt wird. Unmittelbar nach dem Verkleben ist eine Wärmebehandlung bei etwa 200 °C zweckmäßig. Die Erfindung wurde vor allem unter Anwendung des im Handel befindlichen Z-Klebers, dem zum Beispiel 10 bis 70 Volumprozent an Silberteilchen zugesetzt sind, erprobt.
  • 5. Beim Aufdampfen der beiden Metallschichten sind die Aufdampfraten und damit die Rauhigkeit der schließlich erhaltenen Oberfläche der Metallisierung auf die Größe der im Kleber vorgesehenen Silberpartikel derart abzustimmen, daß zwischen der Oberfläche der Silbermetallisierung an der Chip-Rückseite und den im Kleber anwesenden Silberteilchen ein guter Flächenkontakt gewährleistet ist. Zweckmäßig wird man deshalb einen Kleber verwenden, der mit möglichst einheitlichen Silberteilchen, insbesondere zylinderförmigen oder kugelförmigen Leitsilberteilchen versetzt ist, wobei die Teilchengröße auf die Oberflächenrauhigkeit der Silberschicht abgestimmt wird. Die Chromschicht dient dabei als Haftunterlage für die Silberschicht.
The practical implementation of the invention preferably takes place in the following manner:
  • 1. First, the disk-shaped semiconductor body, consisting of monocrystalline silicon, of the semiconductor device to be assembled is removed on the underside to be connected to the base by grinding to such an extent that a total thickness of approximately 180 JLm remains.
  • 2. In a vapor deposition system, the back of the disk-shaped semiconductor body is provided with a 0.1 JL m thick chrome layer at approx. 300 ° C.
  • 3. Immediately afterwards (that is, without opening the vapor deposition system), an approximately 1 J Lm thick silver layer is evaporated onto the chrome layer. It should be noted that even with thinner silver layers, e.g. B. a 0.5 J Lm thick silver layer, still gets good results.
  • 4. The semiconductor device then removed from the vapor deposition system is then fastened by means of the silver-containing adhesive to the housing part provided as a base and consisting of heat-conducting material, in particular a metallic housing base plate. A particularly suitable adhesive is a silicone adhesive (e.g. Z adhesive) which has the required silver particle content and is diluted with about 10% of a suitable solvent before use. Immediately after bonding, heat treatment at about 200 ° C is appropriate. The invention was tested above all using the commercially available Z adhesive, to which, for example, 10 to 70 volume percent of silver particles have been added.
  • 5. When the two metal layers are evaporated, the evaporation rates and thus the roughness of the surface of the metallization finally obtained are to be matched to the size of the silver particles provided in the adhesive in such a way that a good one between the surface of the silver metallization on the back of the chip and the silver particles present in the adhesive Surface contact is guaranteed. It is therefore expedient to use an adhesive which is mixed with the most uniform possible silver particles, in particular cylindrical or spherical conductive silver particles, the particle size being matched to the surface roughness of the silver layer. The chrome layer serves as an adhesive base for the silver layer.

Es empfehlen sich für das Aufdampfen der Chromschicht Abscheidungsgeschwindigkeiten von 3 - 10-5 mm/min bis 4 - 10-5 mm/min, für das Aufdampfen der Silberschicht Aufdampfgeschwindigkeiten von 5 - 10-5 mm/min und ein Kleber, der zylindrische Leitsilberteilchen von 5 µm Durchmesser und 10 µm Länge enthält. Hinsichtlich des Standes der Technik ist zu bemerken, daß aus der US-PS 3 942 244 Elektroden für Halbleitervorrichtungen bekannt sind, wobei die Elektroden aus mehreren übereinander aufgebrachten Metallschichten bestehen. Dabei bildet die an den Halbleiter angrenzende und z. B. aus Aluminium bestehende Metallschicht mit dem Halbleitermaterial eine aus einer Legierung bestehende Schicht. Die äußere Schicht der Elektroden kann z. B. aus Silber bestehen.We recommend deposition rates of 3 - 10- 5 mm / min to 4 - 10-5 mm / min for the vapor deposition of the chrome layer, evaporation rates of 5 - 10- 5 mm / min for the vapor deposition of the silver layer and an adhesive, the cylindrical conductive silver particles of 5 µm in diameter and 10 µm in length. With regard to the prior art, it should be noted that electrodes for semiconductor devices are known from US Pat. No. 3,942,244, the electrodes consisting of a plurality of metal layers applied one above the other. It forms the adjacent to the semiconductor and z. B. consisting of aluminum metal layer with the semiconductor material is an alloy layer. The outer layer of the electrodes can e.g. B. consist of silver.

Andererseits war aus « IBM Techn. Discl. Bull., Vol.13, No 5 (October 1970, S. 1121) die Anwendung einer aus Chrom bestehenden Zwischenschicht für die Haftung einer z. B. aus einer Mischung aus Chrom und Kupfer bestehenden Elektrode auf einer miniaturisierten elektrischen Vorrichtung bekannt. Dabei soll jedoch die Zwischenschicht auch als Barriere zur Unterbindung des Eindringens von Partikeln aus der kupferhaltigen Elektrode in die zu kontaktierende Vorrichtung wirken. Sie wird deshalb so hergestellt, daß die durch Vakuumaufdampfung aufgebrachte Chromschicht zunächst einer kurzen Oxydationsbehandlung zwecks Ausfüllung von Poren in der Chromschicht und dann einem Sputterprozeß zwecks Beseitigung des überschüssigen Oxyds unterzogen wird, bevor die Cu-Cr-Elektrode auf die so entstandene Zwischenschicht aufgebracht wird.On the other hand, from «IBM Techn. Discl. Bull., Vol.13, No 5 (October 1970, p. 1121) the use of an intermediate layer made of chrome for the adhesion of a z. B. known from a mixture of chrome and copper electrode on a miniaturized electrical device. In this case, however, the intermediate layer should also act as a barrier for preventing particles from the copper-containing electrode from penetrating into the device to be contacted. It is therefore manufactured in such a way that the chrome layer applied by vacuum deposition is first subjected to a short oxidation treatment to fill pores in the chrome layer and then to a sputtering process to remove the excess oxide before the Cu-Cr electrode is applied to the intermediate layer thus formed.

Claims (5)

1. A method of mounting a semiconductor device, in particular a monolithically integrated semiconductor circuit, in a housing, in which, using an adhesive consisting of an organic insulating material admixed with silver particles, the semiconductor body (which consists of silicon) of the semiconductor device, has its underside permanently joined to a part of the housing which serves as a support and at the same time as a heat sink, characterised in that, prior to the application of the adhesive, the underside of the semi-conductor body is first covered with a chromium layer and the latter is immediately covered with a silver layer.
2. A method according to Claim 1, characterised in that the thickness of the semiconductor body of the semiconductor device to be installed is reduced, for example, to 180 µm, by a grinding operation on its rear side ; that subsequently in a vapour-deposition unit, a chromium layer of, for example, 0.1 JLm is applied, and a silver layer of, for example, 1 µm is applied on to the chromium layer.
3. A method according to Claim 1 or Claim 2, characterised in that as the adhesive, a silicone adhesive is used.
4. A method according to one of Claims 1 to 3, characterised in that the silver content of the adhesive is set to at least 50 percent by volume.
5. A method according to one of Claims 1 to 4, characterised in that an adhesive is used, the silver content of which is formed by identical silver particles, in particular, of cylindrical or spherical shape.
EP81100276A 1980-01-17 1981-01-15 Method of mounting a semiconductor device in a housing Expired EP0032728B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3001613 1980-01-17
DE3001613A DE3001613C2 (en) 1980-01-17 1980-01-17 Attachment of a silicon semiconductor body containing a monolithically integrated semiconductor circuit to a support using a corresponding method for this purpose

Publications (3)

Publication Number Publication Date
EP0032728A2 EP0032728A2 (en) 1981-07-29
EP0032728A3 EP0032728A3 (en) 1981-08-12
EP0032728B1 true EP0032728B1 (en) 1984-05-23

Family

ID=6092314

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81100276A Expired EP0032728B1 (en) 1980-01-17 1981-01-15 Method of mounting a semiconductor device in a housing

Country Status (4)

Country Link
US (1) US4417386A (en)
EP (1) EP0032728B1 (en)
JP (1) JPS56105643A (en)
DE (1) DE3001613C2 (en)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4454529A (en) * 1981-01-12 1984-06-12 Avx Corporation Integrated circuit device having internal dampening for a plurality of power supplies
US4535350A (en) * 1981-10-29 1985-08-13 National Semiconductor Corporation Low-cost semiconductor device package and process
CA1222071A (en) * 1984-01-30 1987-05-19 Joseph A. Aurichio Conductive die attach tape
US5049434A (en) * 1984-04-30 1991-09-17 National Starch And Chemical Investment Holding Corporation Pre-patterned device substrate device-attach adhesive transfer system
DE3444699A1 (en) * 1984-12-07 1986-06-19 Telefunken electronic GmbH, 7100 Heilbronn ELECTRICAL POWER COMPONENT
KR910004034B1 (en) * 1986-09-18 1991-06-22 미쓰비시전기 주식회사 Cruise control apparatus
EP0264635B1 (en) * 1986-09-25 1991-08-21 Siemens Aktiengesellschaft Electrically conductible adhesive for a large temperature range
JPS63278236A (en) * 1987-02-18 1988-11-15 Mitsubishi Electric Corp Semiconductor device
US5103283A (en) * 1989-01-17 1992-04-07 Hite Larry R Packaged integrated circuit with in-cavity decoupling capacitors
DE4132947C2 (en) * 1991-10-04 1998-11-26 Export Contor Ausenhandelsgese Electronic circuitry
US5569956A (en) * 1995-08-31 1996-10-29 National Semiconductor Corporation Interposer connecting leadframe and integrated circuit
DE59812923D1 (en) 1997-07-23 2005-08-18 Infineon Technologies Ag DEVICE AND METHOD FOR PRODUCING A CHIP SUBSTRATE COMPOUND
US6096576A (en) 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6303986B1 (en) 1998-07-29 2001-10-16 Silicon Light Machines Method of and apparatus for sealing an hermetic lid to a semiconductor die
US6956878B1 (en) 2000-02-07 2005-10-18 Silicon Light Machines Corporation Method and apparatus for reducing laser speckle using polarization averaging
US6707591B2 (en) 2001-04-10 2004-03-16 Silicon Light Machines Angled illumination for a single order light modulator based projection system
US6782205B2 (en) 2001-06-25 2004-08-24 Silicon Light Machines Method and apparatus for dynamic equalization in wavelength division multiplexing
US6747781B2 (en) * 2001-06-25 2004-06-08 Silicon Light Machines, Inc. Method, apparatus, and diffuser for reducing laser speckle
US6829092B2 (en) 2001-08-15 2004-12-07 Silicon Light Machines, Inc. Blazed grating light valve
US6800238B1 (en) 2002-01-15 2004-10-05 Silicon Light Machines, Inc. Method for domain patterning in low coercive field ferroelectrics
US6767751B2 (en) 2002-05-28 2004-07-27 Silicon Light Machines, Inc. Integrated driver process flow
US6728023B1 (en) 2002-05-28 2004-04-27 Silicon Light Machines Optical device arrays with optimized image resolution
US6822797B1 (en) 2002-05-31 2004-11-23 Silicon Light Machines, Inc. Light modulator structure for producing high-contrast operation using zero-order light
US6829258B1 (en) 2002-06-26 2004-12-07 Silicon Light Machines, Inc. Rapidly tunable external cavity laser
US6813059B2 (en) 2002-06-28 2004-11-02 Silicon Light Machines, Inc. Reduced formation of asperities in contact micro-structures
US6714337B1 (en) 2002-06-28 2004-03-30 Silicon Light Machines Method and device for modulating a light beam and having an improved gamma response
US6801354B1 (en) 2002-08-20 2004-10-05 Silicon Light Machines, Inc. 2-D diffraction grating for substantially eliminating polarization dependent losses
US6712480B1 (en) 2002-09-27 2004-03-30 Silicon Light Machines Controlled curvature of stressed micro-structures
US6987600B1 (en) 2002-12-17 2006-01-17 Silicon Light Machines Corporation Arbitrary phase profile for better equalization in dynamic gain equalizer
US6806997B1 (en) 2003-02-28 2004-10-19 Silicon Light Machines, Inc. Patterned diffractive light modulator ribbon for PDL reduction
US6829077B1 (en) 2003-02-28 2004-12-07 Silicon Light Machines, Inc. Diffractive light modulator with dynamically rotatable diffraction plane
DE102006028692B4 (en) * 2006-05-19 2021-09-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Electrically conductive connection with an insulating connection medium

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE510386A (en) * 1951-04-05 1900-01-01
US2809332A (en) * 1953-07-29 1957-10-08 Rca Corp Power semiconductor devices
US2856681A (en) * 1955-08-08 1958-10-21 Texas Instruments Inc Method of fixing leads to silicon and article resulting therefrom
NL6516296A (en) * 1965-12-15 1967-06-16
DE1514668B2 (en) * 1966-01-19 1977-05-12 Siemens AG, 1000 Berlin und 8000 München PROCESS FOR PRODUCING CHROME-SILVER CONTACTS ON SEMICONDUCTOR COMPONENTS
US3942244A (en) * 1967-11-24 1976-03-09 Semikron Gesellschaft Fur Gleichrichterbau Und Elektronik M.B.H. Semiconductor element
US3617821A (en) * 1970-09-17 1971-11-02 Rca Corp High-voltage transistor structure having uniform thermal characteristics
US3770565A (en) * 1972-01-05 1973-11-06 Us Navy Plastic mounting of epitaxially grown iv-vi compound semiconducting films
JPS4940673A (en) * 1972-08-22 1974-04-16
US3896544A (en) * 1973-01-15 1975-07-29 Essex International Inc Method of making resilient electrical contact assembly for semiconductor devices
US3828227A (en) * 1973-04-09 1974-08-06 Sprague Electric Co Solid tantalum capacitor with end cap terminals
JPS5158868A (en) * 1974-11-20 1976-05-22 Hitachi Ltd HANDOTA ISOCHI
DE2619433A1 (en) * 1976-05-03 1977-11-10 Siemens Ag Semiconductor element or integrated circuit bonded to base - has coating protecting system from outgassing of adhesive
DE2743773A1 (en) * 1976-10-04 1978-04-06 Owens Illinois Inc ELECTRICAL DEVICE
US4127424A (en) * 1976-12-06 1978-11-28 Ses, Incorporated Photovoltaic cell array
US4293587A (en) * 1978-11-09 1981-10-06 Zilog, Inc. Low resistance backside preparation for semiconductor integrated circuit chips

Also Published As

Publication number Publication date
JPS56105643A (en) 1981-08-22
DE3001613C2 (en) 1986-04-03
EP0032728A3 (en) 1981-08-12
EP0032728A2 (en) 1981-07-29
US4417386A (en) 1983-11-29
DE3001613A1 (en) 1981-07-23

Similar Documents

Publication Publication Date Title
EP0032728B1 (en) Method of mounting a semiconductor device in a housing
DE69312709T2 (en) SOLDERING PEARL ON CIRCUIT ARRANGEMENT
DE68929282T2 (en) Conductor substrate, film carrier, semiconductor arrangement with the film carrier and mounting structure with the semiconductor arrangement
DE2411259C3 (en) Process for manufacturing integrated circuits
DE69621863T2 (en) Semiconductor arrangement in the size of one or more chips
DE69938582T2 (en) SEMICONDUCTOR ELEMENT, ITS MANUFACTURE, PCB AND ELECTRONIC APPARATUS
DE69602686T2 (en) Method of manufacturing an electrode structure for a semiconductor device
DE68915250T2 (en) Printed circuit boards with self-supporting connection between the sides.
DE19817359B4 (en) Ceramic multilayer circuit and method for its production
DE68915901T2 (en) Multi-layer substrate with conductor tracks.
DE102007017831A1 (en) Semiconductor module, has carrier arranged on semiconductor chip such that one main surface of semiconductor chip faces carrier, where insulating layer and wiring layer covers another main surface of semiconductor chip and carrier
DE112012006812T5 (en) Electronic component and manufacturing process for electronic components
EP0841668B1 (en) Electrical resistor and method of manufacturing the same
DE102005006281A1 (en) Semiconductor device with gold coatings and method of making the same
DE102009040627B4 (en) Semiconductor device and method of manufacturing an electronic system
EP0555668B1 (en) Printed circuit board for electronical power circuit containing power semiconductors
DE3035933C2 (en) Pyroelectric detector and method for manufacturing such a detector
DE2136201C3 (en) Method for attaching metallic leads to an electrical solid-state component
EP0278413A2 (en) Method for making a connection between a bonding wire and a contact pad in hybrid thick-film circuits
WO2004100259A2 (en) Semi-conductor component and method for the production of a semi-conductor component
EP0090820A1 (en) Thin layered electronic circuit and manufacturing method thereof.
DE1953678A1 (en) Circuit carriers for electrical circuit elements and components, as well as processes for its production
DE1764477B1 (en) CERAMIC CAPACITOR
DE69303837T2 (en) Printed circuit board with projecting electrode and connection method
DE2207012C2 (en) Contacting semiconductor device with pN-junction by metallising - with palladium or nickel, alloying in window, peeling and gold or silver electroplating

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Designated state(s): FR GB IT

AK Designated contracting states

Designated state(s): FR GB IT

17P Request for examination filed

Effective date: 19810915

ITF It: translation for a ep patent filed
GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): FR GB IT

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
ITTA It: last paid annual fee
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19941216

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19950116

Year of fee payment: 15

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19960115

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19960115

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19960930

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST