EP0021062A2 - Method for performing a plausibility test concerning successively occurring time information in traffic-light systems - Google Patents

Abstract

1. A method of checking consecutively received items of time information which are transmitted from a central station, in particular a radio transmitter, and which are used in traffic signalling installations in separate locations for the prompt control of these installations in accordance with individual traffic signal programmes, in which a first and a second store (M1, M2) are used, where the first store (M1) serves to receive the item of time information which was in each case the last to have been received, and the item of time information which is transferred from the first store (M1) to the second store (M2) is modified in the second store (M2) in each case by the amount of the time interval between two consecutively received items of information, and in which the contents of the first and second stores (M1, M2) are compared with on another periodically in the timing of the consecutive items of time information, characterized in that, using a third store (M3) in the case of a comparison which results in identity between the contents of the first and second stores (M1, M2), the content of the first store (M1) is transferred to the third store (M3) and only in the event of a comparison which results in non-identity is the content of the first store (M1) transferred to the second store (M2), and that the content of the third store (M3) is used to control the programme sequence of the traffic signalling installation.

Description

The invention relates to a method and a circuit arrangement for carrying out a plausibility check with regard to successively occurring time information, which is carried out by a central location; in particular a radio transmitter, and which are recorded in locally separated traffic signal systems for controlling the timely processing of individual traffic signal programs.

In connection with the detection and elimination of disturbances in the time information in a centrally controlled clock, it is already known (DE-AS 27 01 609) that the time information provided by a central point, for example a transmitter, is to be delivered in coded form to the relevant clock . This time information may include minute, hour, calendar day, weekday, calendar month, year, and other information. The Time information arriving at the centrally controlled clock at parallel or serial intervals is checked for the presence of errors. If errors occur, a switching measure is triggered. In the known method concerned, the error check is repeated cyclically at least until complete and error-free time information is received. When a fault is recognized within a test cycle, the parts of the complete time information which have already been assessed as correct before the fault occurs are stored and / or displayed. However, the parts of this time information that have not yet been evaluated are discarded. When the next complete time information is received, the parts of this time that have already been assessed as correct during the previous test cycle. information with recycled.

A disadvantage of the known method considered above is the fact that a falsification of the respective time information by an interference pulse cannot be easily recognized. This means that in the known method there is no plausibility check of the respective time information.

Although an error correction for radio clocks has already been proposed (DE-AS 16 73 796), each newly determined time information is compared with at least one other time information previously transmitted and / or with time information determined with an additional device, in order to determine deviations to trigger a fault and error detection of the respective actual values from specified target values. However, the overall effort required is relatively high.

The invention has for its object to show a way, as in a method of the aforementioned A plausibility check of the successively occurring time information can be carried out in a relatively simple manner.

The object outlined above is achieved according to the invention in a method of the type mentioned at the outset in that time information recorded and stored by the respective traffic signal system is increased by a fixed time value each time further information is recorded, in that the time information recorded in each case is increased by the time information recorded In each case, the time value which is increased and which is stored in the traffic signal system in question is compared and that the time information recorded last is used only to determine the correspondence between the time information compared with one another for controlling the timely processing of the respectively required traffic signal program.

The invention has the advantage that a plausibility check of successively occurring time information is possible in a relatively simple manner, which are issued by a central point to traffic signal systems that are spatially separated from one another in order to control the timely processing of individual traffic signal programs in these traffic signal systems.

The time value of the time information already stored in the respective traffic signal system is preferably increased by means of a control pulse which occurs together with the respective further time information. This results in the advantage of a particularly simple possibility of changing the time value of the time information already stored in the respective road traffic signal system. When determining a difference between the time information compared with one another, the time information recorded last is expediently used for the corresponding correction of the time information previously recorded. This advantageously ensures that the time information recorded last can be used in the respective traffic signal system, the underlying idea being that an error with regard to the storage and change of the time information occurs more in the individual road traffic signal system than in the course of Transmission of the additional time information.

The frequency of the occurrence of differences between the time information compared with one another is expediently counted, and an error signal is generated when a specific number of differences between the time information compared with each other are determined. This measure has the advantage that permanent errors which occur in the course of the storage and modification of the respective time information can be determined relatively quickly.

To carry out the method according to the invention, it is expedient to use a circuit arrangement which is characterized in that a first memory is connected on the input side to the output of a time information receiver, and that the first memory is connected on the output side to the input side of a second memory via a first logic circuit is connected that the first memory and the second memory on the output side are each connected to the input side of a comparator, that the comparator with its. Inequality of the signals compared with one another with an output carrying a specific output signal Control input of said first logic circuit is connected, that the comparator is connected to a control output of a second logic circuit with an output carrying the same signal compared to one another at a control input of a second logic circuit and that the second logic circuit on the input side at the output of said first memory and on the output side of an input third memory is connected. This results in the advantage of a relatively low outlay in terms of circuitry for carrying out a plausibility check of successively occurring time information which is transmitted from a central location.

In the circuit arrangement described above, the first memory is preferably connected with a release input to a separate output of the time information reception device, to which a pulse occurs in a defined time pattern, which signals the acceptance of the time information present at at least one further output of the time information reception device causes the first memory. This has the advantage that it is possible to make do with a particularly low level of circuitry complexity in order to be able to record and record the current time information in the respective road traffic signal system.

It is also advantageous if the pulse mentioned is used to increase the memory content in said second memory by a certain amount. In this case, one does not need any special additional circuits in order to increase the memory content of the relevant second memory in the desired manner.

Advantageously, the pulse mentioned is also for Control of the release of the comparator exploited. This brings with it the advantage that the comparator for carrying out comparison processes can be effectively controlled at defined times with particularly low circuit complexity.

A counter with its input side is preferably connected to the output of the comparator which emits a certain output signal in the event of inequality. After reaching a certain counter position, the counter emits an error signal at a separate output. This has the advantage that relatively little circuitry can be used to determine whether the circuit arrangement according to the invention is malfunctioning.

The invention is explained in more detail below using an exemplary embodiment with reference to a drawing.

The circuit arrangement shown in the drawing comprises a time information receiving device consisting of a receiver Rec and a decoder Dec connected downstream of this receiver Rec. The receiver Rec may be a radio receiver that is connected on the input side to an antenna Ant, which can be a ferrite antenna, for example. The receiver Rec may be designed so that it receives, for example, the time information respectively transmitted by the time stamp and normal frequency transmitter DCF 77. This time information occurs serially; they include second, minute, hour, calendar day, weekday, calendar month and year information. At this point it should be noted that the present invention is not limited to the serial reception of time information of the type under consideration. Rather, the present invention can also occur in other ways Process below in more detail. For example, the receiver Rec could also be designed in such a way that it records time information supplied to it in parallel on the input side.

The decoder Dec, which converts the time information received from the receiver Rec into a form suitable for subsequent further processing, has two outputs a1 and a2. The output a1 comprises a plurality of individual outputs which are connected via a corresponding multi-core line Lz to a corresponding number of individual inputs of a memory input ez1 of a first memory M1. The actual time information, that is to say the complete time information contained in the time information received by the receiver Rec, appears at the output a1 of the decoder Dec. At the other output a2 of the decoder Dec, pulses may occur in a certain rhythm, which are passed on via a line Lm. If one starts from the reception of the time information transmitted by the transmitter DCF 77, the pulses occurring at the output a2 of the decoder Dec will be so-called minute pulses, which thus occur at the end of each minute of transmission of the transmitter concerned.

The line Lm connected to the output a2 of the decoder Dec is connected to an enable input en1 of the said first memory M1. This memory M1 - which will have such a storage capacity that it can store the time information supplied to its memory input ez1 - is released for storing the time information present at its just mentioned memory input ez1 when its release input en1 has a corresponding pulse as an enable pulse is fed. There are two links on the output side of the memory M1 designated az1 tion circuits Vsl, Vs2 each connected to one input side and a comparator Com connected to its one input side ev1. The logic circuits Vs1, Vs2 and the comparator Com are each connected to the output side az1 of the memory M1 via a plurality of connecting lines with their input sides mentioned. This is indicated by slashes crossing the connecting lines in question. With regard to the logic circuits Vs1, Vs2, it should also be noted that they contain a plurality of logic elements which, as indicated in the drawing, may be formed by AND gates, for example.

The logic circuit Vs1 is connected on the output side to the input side ez2 of a second memory M2 via a corresponding plurality of connecting lines. This memory M2, which has a corresponding memory capacity as the memory M1, is connected to the line Lm already mentioned with a separate control input ec. A pulse supplied to this control input ec of the memory M2 has the effect that the memory content of the memory M2 - ie the time information contained in this memory M2 - is increased by a fixed time value, for example by one minute.

The memory M2 is connected on the output side via a plurality of lines to an input ev2 of the comparator Com having a corresponding number of individual inputs. The comparator Com is connected with a release input em to the line Lm already mentioned above. This control input em of the comparator Com is designed in such a way that the comparator Com is able to carry out a comparison process with respect to the time information at its inputs ev1 and ev2 only when the trailing edge of a pulse occurring on the line Lm occurs.

The comparator Com has two outputs av1 and av2. The comparator Com then outputs a specific output signal (binary signal "H") from the output av1 when it determines a match between the time information supplied to it on the input side for a comparison. For this reason, an equal sign is also indicated at the output av1 of the comparator Com. The comparator Com then outputs a specific output signal (binary signal "H") from its output av2 when it detects an inequality between the time information supplied to it on the input side for a comparison. For this reason, an inequality sign is also indicated at the output av2 of the comparator Com.

The comparator Com is connected with its output av1 to an input of the logic circuit Vs2. With its other output av2, the comparator Com is connected to an input of the logic circuit Vs1. In response to the output of a specific output signal (binary signal "H") from the respective output av1 or av2 of the comparator Com, either the logic circuit Vs2 or the logic circuit Vs1 is made capable of being transmitted for the transmission of time information supplied to it on the input side.

The logic circuit Vs2 is connected on the output side via a plurality of lines to the memory input side ez3 of a third memory M3. As will be seen, this memory M3 contains the current time information for the circuit arrangement under consideration. The memory M3 is connected to an enable input en3 in the present case at the output of a counter Cnt, which is connected on the input side to the output av2 of the comparator Com.

The memory M3 is on the output side at a control input ed connected to a control device Con, which controls the handling of traffic signal programs in a traffic signal system to which it belongs. From this traffic signal system, only two signal generators Sg1 and Sg2 are indicated, to which corresponding control signals are supplied by the control device Con. These signal transmitters may each contain, for example, a green signal lamp (indicated by a circle with a vertical line in the drawing) and a red signal lamp (indicated by a circle with a horizontal line in the drawing). The control device Con is connected with an input / output eam to a program memory PROM, which contains the traffic signal programs to be used in each case, which are selected in accordance with the time information supplied by the memory M3 and processed in the control device Con. The programs in question can be permanently stored in the program memory PROM, or they can be supplied to the program memory PROM from time to time by a traffic control center superordinate to several traffic signal systems. It is important for the present case, however, that the program memory PROM contains different traffic signal programs, which have to be processed at different times for the traffic signal system in question. In the simplest case, the program memory PROM can contain, for example, a holiday traffic signal program and a weekday traffic signal program in order to do justice to the different traffic conditions in the area of the associated traffic signal system on public holidays and weekdays.

The operation of the arrangement shown in the drawing is explained in more detail below. For this purpose it is assumed that there is initially no time information in the memories M1, M2 and M3. Will now If time information is received by the receiver Rec, this time information is stored in the memory M1. At the same time, the content of the memory M2 is increased by a certain fixed time value. Since the memory content of the memory M2 was initially zero, this memory M2 will then only contain the time value provided for an increase. This time value is compared in the comparator Com at the end of the pulse occurring on the line Lm with the time information contained in the memory M1. Since it can be assumed that the comparator Com detects an inequality between the signals compared with one another, it outputs a specific output signal (binary signal "H") at its output av2. The occurrence of this output signal causes the logic circuit Vs1 to be transferable for the time information output by the memory M1. The relevant time information thus enters the memory M2, which then has the same memory content as the memory M1. However, the comparator Com is no longer effective at this point in time in order to compare the corrected memory content of the memory M2 with the memory content of the memory M1. However, the comparator Com carries out a corresponding comparison if a further pulse has been emitted from the output a2 of the decoder Dec via the line Lm. This is the case after the receiver Rec has received further time information which has also been decoded accordingly by the decoder Dec. In this case, the occurrence of a pulse on the line Lm causes the new time information now present to be stored in the memory M1. In addition, the pulse occurring on the line Lm causes the "old" time information still contained in the memory M2 to be increased by a fixed time value, for example by one minute. The ratios are chosen so that the specified time value equal to the difference between is two time information recorded successively by the receiver Rec.

The comparator Com will now determine a match between the signals or time information it has compared with one another as a result of the last considered processes in the memories M1 and M2. As a result, the logic circuit Vs2 then becomes capable of being transmitted, as a result of which the "new" time information still contained in the memory M1 is stored in the memory M3 as current time information. Thus, the time information required for the selection and processing of a traffic signal program from the program memory PROM is available for the control device Con of the traffic signal system. This time information has been subjected to a plausibility check. As explained, the time information stored in the memory M1 is only stored in the memory M3 as current time information if it has a fixed relationship to the time information previously recorded and stored in the memory M2.

If the comparator Com determines in the course of carrying out a comparison between two pieces of time information that these are not in the previously mentioned fixed relationship to one another - that is, they are unequal - it in turn causes the logic circuit Vs1 to be made transferable. The time information contained in the memory M1 is thus stored in the memory M2, so that both memories M1 and M2 then again contain the same time information stored.

The counter Cnt connected to the output av2 of the comparator Com counts the occurrence of any inequality between the time information compared with each other. The arrangement may be so be that when a certain counter position is reached, for example at counter position 2, the counter Cnt emits an error signal which is used, for example, to block or erase the memory M3. The counter Cnt can be connected to the output 'av1 of the comparator Com with a reset input.

The procedure explained above for the circuit arrangement shown in the drawing thus ensures that only time information is provided for the control device Con of the traffic signal system with respect to which there is a plausibility that it is also correct. In this way, errors occurring either in the circuit arrangement under consideration or in the course of the transmission of the respective time information can be detected which not only cause time information to be falsified but which cause time information to be falsified several times.

Finally, it should be noted that a microprocessor or a microcomputer can be used to implement the circuit arrangement explained.

Claims (9)

1. A method for carrying out a plausibility check regarding successively occurring time information, which is issued by a central point, in particular a radio transmitter, and which is recorded in locally separated traffic signal systems for controlling the timely processing of individual traffic signal programs, characterized in that one recorded by the respective traffic signal system and stored time information is increased by the recording of each additional time information, in each case by a fixed time value, that the respectively recorded further time information is compared with the time information, which is increased in its time value and stored in the traffic signal system in question, and that when determining a match between the time information compared with one another the most recently recorded time information for controlling the timely processing of the required traffic signal pr ogramms is used. 2. The method according to claim 1, characterized in that the increase in the time.. Value of the time information already stored in the respective traffic signal system is carried out by means of a control pulse which occurs together with the respective further time information. 3. The method according to claim 1 or 2, characterized in that when determining a difference between the time information compared with each other, the last time information recorded is used for the corresponding correction of the previously recorded time information. 4. The method according to any one of claims 1 to 3, characterized in that the frequency of the occurrence of differences between the time information compared in each case is counted and that an error signal is generated when determining a certain number of differences between the time information compared in each case. 5. Circuit arrangement for carrying out the method according to any one of claims 1 to 4, characterized in that at the output of a time information receiving device (Rec, Dec) a first memory (M1) is connected on the input side, that the first memory (M1) on the output side a first logic circuit (Vs1) is connected to the input side of a second memory (M2), that the first memory (M1) and the second memory (M2) are each connected on the output side to the input side (ev1, ev2) of a comparator (Com), that the comparator (Com) is connected with its output (av2) carrying a certain output signal ("H") when the compared signals are inequality with a control input of said first logic circuit (Vs1), that the comparator (Com) with one with equality the signals compared to each other a certain output signal ("H") leading output (av1) at a control input of a second logic circuit (V s2) is connected and that the second logic circuit (Vs2) is connected on the input side to the output (az1) of said first memory (M1) and on the output side to the input side (ez3) of a third memory (M3). 6. Circuit arrangement according to claim 5, characterized in that the first memory (M1) with a release input (en1) is connected to a separate output (a2) of the time information reception device (Rec, Dec), at which a pulse occurs in a defined time pattern, which signals the acceptance of the at least one further output ( a1) of the time information receiving device (Rec, Dec) causes existing time information in the first memory (M1). 7. Circuit arrangement according to claim 6, characterized in that the pulse in question is used to increase the memory content in said second memory (M2) by a certain amount in each case. 8. Circuit arrangement according to claim 6 or 7, characterized in that said pulse for controlling the release of the comparator (Com) is used. 9. Circuit arrangement according to one of claims 5 to 8, characterized in that at the inequality in a certain output signal ("H") output (av2) of the comparator (Com) a counter (Cnt) is connected with its input side and that Counter (Cnt) emits an error signal ("H") at a separate output after reaching a certain counter position.

Images