EP0021062B1 - Method for performing a plausibility test concerning successively occurring time information in traffic-light systems - Google Patents

Abstract

1. A method of checking consecutively received items of time information which are transmitted from a central station, in particular a radio transmitter, and which are used in traffic signalling installations in separate locations for the prompt control of these installations in accordance with individual traffic signal programmes, in which a first and a second store (M1, M2) are used, where the first store (M1) serves to receive the item of time information which was in each case the last to have been received, and the item of time information which is transferred from the first store (M1) to the second store (M2) is modified in the second store (M2) in each case by the amount of the time interval between two consecutively received items of information, and in which the contents of the first and second stores (M1, M2) are compared with on another periodically in the timing of the consecutive items of time information, characterized in that, using a third store (M3) in the case of a comparison which results in identity between the contents of the first and second stores (M1, M2), the content of the first store (M1) is transferred to the third store (M3) and only in the event of a comparison which results in non-identity is the content of the first store (M1) transferred to the second store (M2), and that the content of the third store (M3) is used to control the programme sequence of the traffic signalling installation.

Description

The invention relates to a method according to the preamble of the claim.

Such a method is known from DE-A-1 416 202 without reference to traffic signal systems.

In the known method, the periodically transmitted time information is initially recorded in a first memory at the receiving end. Before new time information is stored in the first memory, the time information previously held in the first memory is transferred to a second memory and changed there adding the time period that elapses between two time information transmissions. The contents of the two memories are then compared. If this comparison shows agreement, a counter is switched on. If the memory comparison does not match the contents of the memory, the counter is reset. Only when a certain counter reading has been reached is this evaluated as receiving undisturbed time information and now the second memory is separated from the memory comparison and the content of the second memory is changed autonomously in the rhythm of the time periods between two time information by the amount of this time period. The respective content of the second memory then serves as time information that can be used by the receiver.

If the content of the second memory is changed, faults can occur.

The object of the present invention is therefore to develop a method of the type mentioned at the outset in such a way that time information received and assessed as correct is available for controlling the traffic signal system.

According to the invention, this object is achieved by an embodiment of the method which corresponds to the characterizing features of the patent claim.

An embodiment of the invention is explained in more detail below with reference to a figure.

The circuit arrangement shown in the drawing comprises a time information receiving device consisting of a receiver Rec and a decoder Dec connected downstream of this receiver Rec. The receiver Rec may be a radio receiver that is connected on the input side to an antenna Ant, which can be a ferrite antenna, for example. The receiver Rec may be designed such that it receives, for example, the time information respectively transmitted by the time stamp and normal frequency transmitter DCF 77. This time information occurs serially; it includes second, minute, hour, calendar day, weekday, calendar month and year information. At this point it should be noted that the present invention is not limited to the serial reception of time information of the type under consideration. Rather, the present invention can also process time information that occurs in a different manner in the manner to be considered in more detail below. For example, the receiver Rec could also be designed in such a way that it records time information supplied to it in parallel on the input side.

The decoder Dec, which converts the time information received from the receiver Rec into a form suitable for subsequent further processing, has two outputs a1 and a2. The output a1 comprises a plurality of individual outputs, which are connected via a corresponding multi-core line Lz to a corresponding number of individual inputs of a memory input ez1 of a first memory M1. The actual time information, that is to say the complete time information contained in the time information received by the receiver Rec, appears at the output a1 of the decoder Dec. At the other output a2 of the decoder Dec, pulses may occur in a certain rhythm, which are passed on via a line Lm. If one starts from the reception of the time information transmitted by the transmitter DCF 77, the pulses occurring at the output a2 of the decoder Dec will be so-called minute pulses, which thus occur at the end of each minute of the transmitter concerned.

The line Lm connected to the output a2 of the decoder Dec is connected to an enable input en1 of the said first memory M1. This memory M1 - which will have such a storage capacity that it will be able to store the time information supplied to its memory input ez1 - is released for storing the time information present at its just mentioned memory input ez1 when its release input en1 has a corresponding pulse as an enable pulse is fed. Two logic circuits Vs1, Vs2, each with one input side and a comparator Com, with its one input side ev1, are connected to the output side of the memory M1 designated az1. The logic circuits Vs1, Vs2 and the comparator Com are each connected to the output side az1 of the memory M1 via a plurality of connecting lines with their input sides mentioned. This is indicated by slashes crossing the connecting lines in question. With regard to the logic circuits Vs1, Vs2, it should also be noted that these contain a plurality of logic elements which - as indicated in the drawing - may be formed by AND gates, for example.

The logic circuit Vs1 is connected on the output side to the input side ez2 of a second memory M2 via a corresponding plurality of connecting lines. This memory M2, which has a corresponding memory capacity as the memory M1, is with ei nem separate control input ec connected to the already mentioned line Lm. A pulse supplied to this control input ec of the memory M2 has the effect that the memory content of the memory M2 - that is to say the time information contained in this memory M2 - is increased by a fixed time value, for example by one minute.

The memory M2 is connected on the output side via a plurality of lines to an input ev2 of the comparator Com having a corresponding number of individual inputs. The comparator Com is connected with a release input em to the line Lm already mentioned above. This control input em of the comparator Com is designed in such a way that the comparator Com is able to carry out a comparison process with respect to the time information at its inputs ev1 and ev2 only when the trailing edge of a pulse occurring on the line Lm occurs.

The comparator Com has two outputs av1 and av2. The comparator Com then outputs a certain output signal (binary signal “H”) from the output av1 when it determines a match between the time information supplied to it on the input side for a comparison. For this reason, an equals sign is also indicated at the output av1 of the comparator Com. The comparator Com then outputs a specific output signal (binary signal “H”) from its output av2 when it detects an inequality between the time information supplied to it on the input side for a comparison. For this reason, an inequality sign is also indicated at the output av2 of the comparator Com.

The comparator Com is connected with its output av1 to an input of the logic circuit Vs2. With its other output av2, the comparator Com is connected to an input of the logic circuit Vs1. When a certain output signal (binary signal “H”) is emitted from the respective output av1 or av2 of the comparator Com, either the logic circuit Vs2 or the logic circuit Vs1 is made capable of being transmitted for the transmission of time information supplied to it on the input side.

The logic circuit Vs2 is connected on the output side via a plurality of lines to the memory input side ez3 of a third memory M3. As will be seen, this memory M3 contains the current time information for the circuit arrangement under consideration. The memory M3 is connected to an enable input en3 in the present case at the output of a counter Cnt, which is connected on the input side to the output av2 of the comparator Com.

The memory M3 is connected on the output side to a control input ed of a control device Con, which controls the processing of traffic signal programs in a traffic signal system to which it belongs. From this traffic signal system, only two signal generators Sg1 and Sg2 are indicated, to which corresponding control signals are supplied by the control device Con. These signal transmitters may each contain, for example, a green signal lamp (indicated by a circle with a vertical line in the drawing) and a red signal lamp (indicated by a circle with a horizontal line in the drawing). The control device Con is connected to an input / output eam with a program memory PROM which contains the traffic signal programs to be used in each case, which are selected in accordance with the time information supplied by the memory M3 and processed in the control device Con. The programs in question can be permanently stored in the program memory PROM, or they can be supplied to the program memory PROM from time to time by a traffic control center superordinate to several traffic signal systems. It is important for the present case, however, that the program memory PROM contains different traffic signal programs, which have to be processed at different times for the traffic signal system in question. In the simplest case, the program memory PROM can contain, for example, a holiday traffic signal program and a weekday traffic signal program in order to do justice to the different traffic conditions in the area of the associated traffic signal system on public holidays and weekdays.

The operation of the arrangement shown in the drawing is explained in more detail below. For this purpose it is assumed that there is initially no time information in the memories M1, M2 and M3. If time information is now received by the receiver Rec, this time information is stored in the memory M1. At the same time, the content of the memory M2 is increased by a certain fixed time value. Since the memory content of the memory M2 was initially zero, this memory M2 will then only contain the time value provided for an increase. This time value is compared in the comparator Com at the end of the pulse occurring on the line Lm with the time information contained in the memory M1. Since it can be assumed that the comparator Com detects an inequality between the signals compared with one another, it outputs a specific output signal (binary signal “H”) at its output av2. The occurrence of this output signal has the effect that the logic circuit Vs1 is capable of being transmitted for the time information provided by the memory M1. The relevant time information thus enters the memory M2, which then has the same memory content as the memory M1. At this point in time, the comparator Com is no longer effective in order to compare the corrected memory content of the memory M2 with the memory content of the memory M1 chen. However, the comparator Com carries out a corresponding comparison if a further pulse has been emitted from the output a2 of the decoder Dec via the line Lm. This is the case after the receiver Rec has received further time information which has also been decoded accordingly by the decoder Dec. In this case, the occurrence of a pulse on the line Lm causes the new time information now present to be stored in the memory M1. In addition, the pulse occurring on the line Lm causes the "old" time information still contained in the memory M2 to be increased by a fixed time value, for example by one minute. The ratios are chosen such that the specified time value is equal to the difference between two time information items recorded in succession by the receiver Rec.

The comparator Com will now determine a match between the signals or time information it has compared with one another as a result of the last considered processes in the memories M1 and M2. The result of this is that the logic circuit Vs2 then becomes capable of transmission, as a result of which the “new” time information still contained in the memory M1 is stored in the memory M3 as current time information. The time information required for the selection and processing of a traffic signal program from the program memory PROM is thus available for the control device Con of the traffic signal system. This time information has been subjected to a plausibility check. As explained, the time information stored in the memory M1 is only stored in the memory M3 as current time information if it has a fixed relationship to the time information previously recorded and stored in the memory M2.

If the comparator Com determines in the course of carrying out a comparison between two pieces of time information that these are not in the previously mentioned fixed relationship to one another - that is to say are unequal - this in turn causes the logic circuit Vs1 to be made transferable. The time information contained in the memory M1 is thus stored in the memory M2, so that both memories M1 and M2 then again contain the same time information stored.

The occurrence of any inequality between the time information compared with each other is counted by the counter Cnt connected to the output av2 of the comparator Com. The arrangement may be such that the counter Cnt emits an error signal when a certain counter position is reached, for example when the counter position 2 which is used, for example, to block or delete the memory M3. The counter Cnt can be connected to the output av1 of the comparator Com with a reset input.

The procedure explained above for the circuit arrangement shown in the drawing thus ensures that only time information is provided for the control device Con of the traffic signal system with respect to which there is a plausibility that it is also correct. In this way, errors occurring either in the circuit arrangement under consideration or in the course of the transmission of the respective time information can be detected which not only cause time information to be falsified but which cause time information to be falsified several times.

Finally, it should be noted that a microprocessor or a microcomputer can be used to implement the circuit arrangement explained.

Claims (1)

1. A method of checking consecutively received items of time information which are transmitted from a central station, in particular a radio transmitter, and which are used in traffic signalling installations in separate locations for the prompt control of these installations in accordance with individual traffic signal programmes, in which a first and a second store (M1, M2) are used, where the first store (M1) serves to receive the item of time information which was in each case the last to have been received, and the item of time information which is transferred from the first store (M1) to the second store (M2) is modified in the second store (M2) in each case by the amount of the time interval between two consecutively received items of information, and in which the contents of the first and second stores (M1, M2) are compared with one another periodically in the timing of the consecutive items of time information, characterised in that, using a third store (M3) in the case of a comparison which results in identity between the contents of the first and second stores (M1, M2), the content of the first store (M1) is transferred to the third store (M3) and only in the event of a comparison which results in non-identity is the content of the first store (M1) transferred to the second store (M2), and that the content of the third store (M3) is used to control the programme sequence of the traffic signalling installation.

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