Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
  • H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
  • H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
  • H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
  • H03J5/0254—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being transfered to a D/A converter
  • H03J5/0263—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being transfered to a D/A converter the digital values being held in an auxiliary non erasable memory
• • G—PHYSICS
  • G04—HOROLOGY
  • G04G—ELECTRONIC TIME-PIECES
  • G04G15/00—Time-pieces comprising means to be operated at preselected times or after preselected time intervals
  • G04G15/006—Time-pieces comprising means to be operated at preselected times or after preselected time intervals for operating at a number of different times

Definitions

• the present invention relates to television systems including apparatus for programming the television system so that it is automatically tuned to preselected channels at corresponding future times.
• a variety of so-called television “programmers” or “schedulers” have recently been proposed for programming a television system such as a television receiver or video tape recorder so that it is automatically tuned to preselected channels at corresponding future times. These systems have necessitated adding control apparatus to the television system for entering and verifying the information related to the future selections. Since many present day television receivers already include a calculator-like keyboard for generating binary signals representing channel numbers of channels to be tuned by a digital tuuer portion of the receiver and a receiver characteristic such as volume to be controlled by a signal processing portion of the receiver, it is desirable to minimize the cost and complexity of additional apparatus for a scheduling feature so that the scheduler portion be capable of utilizing the same keyboard, without any additional control devices for entering and verifying scheduling information.
• scheduler apparatus in which the same keyboard has a multiplicity of functions, it is desirable to provide, prompt features which suggest or remind a viewer of which operational steps to follow in the various operating modes, again desirably without the necessity of additional apparatus. Finally, it is desirable that such scheduler apparatus operate in a manner which tends to reduce the possibility of entry of information which is improper due to operator error.
• a television system including programmable means for at least temporarily storing binary signals representing information to be selected by a user, digital tuner means for tuning the television system to various channels identified by respective channel numbers in a predetermined range of numbers in response to binary signals representing said channel numbers and keyboard means including a plurality of digit keys for normally generating binary signals representing said channel numbers in response to the operation of said digit keys by the user, control means are provided which are responsive to the operation of at least one of the digit keys to generate binary signals representing channel numbers within the predetermined range of numbers for causing the digital tuner means to tune the television system to respective channels and which are responsive to the operation of at least one of the digit keys to generate a predetermined number not within said predetermined range for enabling the programmable means to receive binary signals generated in response to the subsequent operation of the digit keys.
• a television system including programmable means for at least temporarily storing binary signals representing information selected by a user, digital tuning means for tuning the television system to various channels identified by respective channel numbers in response to binary signals representing the channel numbers to thereby generate an IF signal having components representing picture and audio information, signal processing means for deriving picture and audio signals from the components of the IF signal, first power supply means for selectively coupling and decoupling operating power to at least one of the digital tuner means and the signal processing means to thereby establish an on condition of the television system and an off condition of the television system, keyboard means including digit keys for normally generating binary signals representing the channel numbers in response to the operation of said digit keys by the user, there is provided second power supply means and control means receiving operating power from said second power supply means and being coupled to said first power supply means for enabling binary signals generated in response to the operation of the digit keys to be coupled to said digital tuner means when the television system is in said on condition and for enabling binary signals generated in response to the operation of the a
• FIGURE 1 is a block diagram of a television receiver including a scheduler constructed in accordance with the present invention
• FIGURE 2 is a mechanical layout of the keyboard utilized to control the receiver shown in FIGURE 1 in its various modes of operation;
• FIGURE 3 is a table indicating the binary signals generated when each of the keys of the keyboard shown in FIGURE 2 are operated;
• FIGURES 4 and 4a-4k indicate how a display is utilized to convey information to a user during the various operating modes of the receiver shown in FIGURE 4;
• FIGURE 5 is a block diagram of the organization of the RAM memory portion of the scheduler shown in FIGURE 1;
• FIGURE 6 is a simplified flow chart indicating the relationship of the various detailed flow charts of FIGURES 7-29;
• FIGURES 7-29 are detailed flow charts indicating the manner in which binary signals are coupled between various portions of the television receiver shown in FIGURE 1 during its various operating modes.
• the television receiver shown in FIGURE 1 includes a chassis 12 comprising the tuning and signal processing portions of the receiver.
• chassis 12 includes a digital tuner 14 which converts RF signals received from a source such as an antenna 16 to IF signals.
• the IF signals include carriers bearing video, color and sound information.
• Signal processing unit 18 separates, amplifies and otherwise processes the various components of the IF signal to derive video, color and sound signals.
• the video and color signals are coupled to a picture tube 20.
• the sound information is coupled through a volume level control unit 22 to a speaker 24.
• Chassis 12 also includes a deflection portion, not shown. Power for the various portions of the receiver is derived from a source of 60 Hz line voltage indicated by a power plug 26.
• the line voltage is coupled through an on/off switching unit 28 to a chassis power supply unit 30 which derives the DC operating voltages for chassis 12.
• keyboard 32 includes ten digit keys labelled 0 through 9, an up ( ⁇ ) key and a down ( ⁇ ) key.
• ⁇ up
• ⁇ down
• keyboard strobe signal When any one of the keys is operated by depressing it, four binary data signals are generated followed by a binary, keyboard strobe signal.
• the various data signals generated by the operation of each key and their hexidecimal code equivalent, are indicated in FIGURE 3.
• the keyboard strobe signal when a binary "1" indicates that the data signals have been generated and processed.
• the binary signals generated by keyboard 32 are coupled to a microcomputer 34.
• the structure of microcomputer 34 will be described in detail below.
• Microcomputer 34 includes a control portion 100 which controls arithmetic and logical operations, decision making operations and the coupling of binary signals within microcomputer 34 to portions of the receiver outside microcomputer 34.
• Control portion 100 operates according to a set of instructions permanently stored in binary format in respective memory locations of a ROM (Read Only Memory) 120.
• a RAM (Random Access Memory) 130 contains a number of memory portions or registers for temporarily storing binary signals representing, among others as will subsequently be explained, information related to the key of keyboard 32 which was last operated, the present time, the present and future times and channel numbers of corresponding channels to be tuned at those future times.
• the binary signals stored in RAM 130 are processed under the control of control portion 100.
• a set of bidirectional input/output ports couple binary signals between microcomputer 34 and the remainder of the receiver under the control of control portion 100.
• Microcomputer 34 is responsive to the binary signals generated when keys of keyboard 32 are operated to establish and control various operating modes of the receiver.
• the operating modes of the receiver include: a normal mode in which the operation of the digit keys of keyboard 32 causes the television receiver to be turned on and off and channels to be selected and operation of the up and down keys causes the volume level to be increased and decreased, respectively; a clock setting mode in which operation of the digit keys causes a counter portion of RAM 130 to be set to the present day and time of day; a programming mode in which operation of the digit keys causes information pertaining to future selections, i.e., future times and channel numbers of channels to be tuned at those times, to be stored in a portion of RAM 130; an editing mode in which operation of the digit keys causes information stored in RAM 130 corresponding to future selections to be reviewed for verification; and a deleting mode in which operation of the digit keys and the volume down key causes an unwanted future selection stored in RAM 130 to be deleted.
• Microcomputer 34 also controls a scheduling mode during which the future time information of each
• Binary signals generated by microcomputer 34 are coupled to various portions of the receiver to control its operation during the various modes identified above.
• On/off switching unit 28 is responsive to a binary signal generated by microcomputer 34 to selectively couple or decouple operating voltage from chassis 12 and thereby control when the receiver proper (i.e., the portion of the receiver excluding microcomputer 34) is on or off.
• a channel number register 36 stores binary signals generated by microcomputer 34 representing the channel number of a channel manually selected by means of keyboard 32 during the normal mode or automatically selected under the control of microcomputer 34 during the scheduling mode.
• the binary signals stored in channel number register 36 control the frequency of a local oscillator signal generated by digital tuner 14 to tune the receiver to a selected channel.
• channel number register 36 may desirably be coupled to a programmable frequency divider for determining the loop frequency of a phase locked loop tuning system.
• a display 40 is responsive to binary signals generated by microcomputer 34 and suitably amplified by drivers, generally designated as 38, to selectively display the channel number of a selected channel or the present time during the normal mode.
• display 40 includes four seven-segment arrays, as indicated in FIGURE 4, for normally displaying the decimal digits between 0-9 and an asterisk (*) symbol to indicate whether the present time is AM or PM.
• Display 40 is also responsive to binary signals generated by microcomputer 34 to display information stored or to be stored in RAM 130 during the clock setting, programming, editing and deleting modes.
• display 40 is responsive to binary signals generated by microcomputer 34 to display prompt symbols, typically including at least one letter, as indicated in FIGURES 4a-4k, to suggest the next operation to be performed by a user.
• a low pass filter 42 is responsive to a pulse signa generated by microcomputer 34 during the normal mode to generate a DC control signal for controlling the volume level Specifically, the DC control signal controls the gain of volume control unit 22 and thereby controls the volume level.
• keyboard 32 is the exclusive means by which the receiver is turned on and off, channel selections are made and the volume level is changed and, in addition, is the exclusive means by which the other user controlled modes of operation, i.e., the clock setting, programming, editing and deleting modes of operation are initiated and by which information pertaining to these modes is entered.
• the other user controlled modes of operation i.e., the clock setting, programming, editing and deleting modes of operation are initiated and by which information pertaining to these modes is entered.
• FIGURE 4a When plug 26 is first plugged in, display 40 will display — :— (FIGURE 4a) indicating to a user that the clock must be set.
• the clock setting operation is explained below.
• the user selects .a predetermined channel number within a range of legal channel numbers, e.g., in the United States any of the channel numbers between 2 and 83 corresponding to the broadcast carriers designated by the FCC (Federal Communications Commission).
• the user first hits the digit key corresponding to the tens digit of the channel number and then hits the digit key corresponding to the units digit of the channel number. For example, to select channel 23, the user hits digit' key 2 then digit key 3.
• display 40 displays 23 (FIGURE 4j).
• any channel number below 10 the user must first hit a 0 since the tens digit of these channel numbers is 0.
• the user hits digit key 0 and then digit key 9. If the user does not complete the channel number by only hitting a first digit key, the display will display the first digit followed by a dash (-), e.g., 2- (FIGURE 4i). If the viewer selects an illegal channel number other than 00, e.g., 93, the receiver will not respond and the display remains as it was.
• the user selects illegal channel number 00. If the clock has been set, the display will display the present time (FIGURE 4c). The asterisk in the upper right hand corner of the display indicates PM and its absence indicates AM. If the clock has not been set, the display will display —:— (FIGURE 4a).
• the user When the receiver is on, the user may increase the volume by hitting the up ( ⁇ ) key. To decrease the volume, the user hits the down ( ⁇ ) key.
• the symbol VOL is printed next to the up and down keys to identify its volume changing function.
• the user To initiate the clock setting, programming, editing or deleting modes, the user always starts by selecting the illegal channel number 00. This has two effects. First, it causes the tuner, signal processing and deflection portions of the receiver to be turned off. Since the keys have different functions in the clock setting, programming, editing and deleting modes than in the normal mode, turning the receiver off tends to reduce confusion to a user and reduces the possibility of entering erroneous information. In addition, since the modes in which information is entered or reviewed may be relatively time consuming (as will be seen later, as many as 22 selections may be scheduled for future viewing), turning the receiver proper off in these modes reduces energy consumption.
• volume up ( ⁇ ) key which is also labelled START.
• display 40 will display a dash (-) indicating that he may start to enter data.
• the user hits 0 digit key which is identified by the letters CS (Clock Set) to initiate the clock setting mode.
• display 40 displays CS- (FIGURE 4b) verifying to the user that the receiver is indeed in the clock setting mode.
• each digit key between 1 and 7 is also labelled with a corresponding day of week.
• the dash is replaced by the number in the display of the day of the week so that CSX, where X is the number of the day of the week, is displayed. If the viewer hits 0, 8 or 9 when CS- is displayed, the display will not change since there is no day of the week corresponding to the numbers 0, 8 or 9. .Approximately 1 second after the display CSX, the display will automatically change to —:— (FIGURE 4a).
• the user then sequentially hits the digit keys corresponding to the tens digit of the present hour, units digit of the present hour, tens digit of the present minute and units digit of the present minute.
• the dashes of the —:— display are replaced in sequence by a respective digit.
• the 4 digit number corresponding to the present time is displayed (FIGURE 4c) and the asterisk (*) in the right hand corner of the display flashes prompting the user to select AM or PM.
• AM is selected by hitting the 3 digit key, which is also labelled AM
• PM is selected by hitting the 6 digit key, which is also labelled PM. If AM has been selected, the asterisk extinguishes and if PM has been selected, the asterisk remains displayed.
• the user now hits volume down ( ⁇ ), which is also labelled END.
• the display is briefly extinguished and then returns.
• the clock setting procedure may take a few seconds, it may be advisable to set the present time slightly ahead and hit the END key when that time occurs.
• Certain precautions in the clock setting operation have been provided for avoiding the entry of erroneous information. That is, no time can be entered which does not correspond to an actual time. For example, if the user hits any digit key other than the 0 or 1 digit key for the tens digit of the hour, no entry will be made and the display will correspondingly remain unchanged. Similarly, if the units digit of hours is selected to greater than 2 or the tens digit of minutes is selected to be greater than 6, no entry will be made and the display will not change.
• the user To program the receiver to automatically tune to preselected channels at corresponding preselected future times during the scheduling mode, the user hits the 0 digit key twice in succession to turn off the receiver proper and then hits the volume up ( ⁇ ) key. At this point, a dash (-) is displayed as in the clock, setting mode. To initiate the programming mode, the user then hits any digit key between 1 and 8 corresponding to the future day he wishes to schedule the receiver. It is noted that in addition to the 1 through 7 digit keys being identified by corresponding days of the week, the 8 digit key is identified by the symbol M-F.
• PrX (FIGURE 4e), where "X" is the number of the day (including 8 for Monday through Friday). This prompt symbol indicates to a user that the receiver is in the programming mode and that day X is to be scheduled.
• the minutes entered by a user are rounded off to the nearest hour or half hour. That is, if the minutes entry is less than one quarter of an hour, the time is rounded off to the hour. If the minutes entry is greater than three quarters of an hour, the previously entered hour is increased to the next hour. If the minutes entry is between one quarter of an hour and three quarters of an hour, the time is rounded off to the previously entered hour plus one half hour. This is so because most programs occur on the hour and half hour. The user then enters either AM or PM as in the clock setting mode.
• —C is displayed (FIGURE 4f). This prompts the viewer to sequentially hit two digit keys corresponding to the channel as during normal channel selection.
• XXC is displayed, where the X's represent the two digits.
• the symbol Pris displayed thereby prompting the user to begin scheduling the next day as described above. At this point, he may schedule another selection for the same day or a selection for another day or Monday through Friday.
• selections may be programmed out of time sequence as to day and time of day and the user therefore need not worry about entering information in the proper time sequence. If the user attempts to schedule more selections than there is room for in RAM 130, the display will display the word "Full" (FIGURE 4k) thereby informing him that he must delete an existing selection before entering any newones. When the user has made all the selections he cares to, he hits the down key. At this point, the present time of day is again displayed. It is also noted that the receiver may be simply programmed to turn off at predetermined times by selecting channel number 00 for that time during the programming mode. Similarly, the receiver may be programmed to turn on at preselected times by selecting any proper channel number for that time during the programming mode.
• the user sequentially hits the 0 digit key twice in succession to turn the receiver proper off, hits the up key as in the clock setting and programming modes, and then hits the 9 digit key which is also identified by the word EDIT.
• Ed(FIGURE 4g) is displayed indicating to the user that the receiver is in the editing mode and prompting him to select the future day he wishes to review.
• the user selects the day by hitting the appropriate digit key 1-7 or Monday through Friday by hitting digit key 8.
• the first time at which a selection has been made will be displayed and after approximately 1 second the channel number of the channel selected at that time will be displayed as XXC, where the X's represent the channel number.
• the channel selected for that future time will not be displayed until approximately 1. seconds after he releases the key.
• the user may examine the next selection in that day by again hitting the digit key of that day.
• Ed- is again displayed prompting the user to review another day by hitting the digit key corresponding to that day. If there are no selections for a particular day, when the user hits the digit key for that day, Ed- remains displayed. To terminate the editing mode, the viewer hits the down key. Thereafter, the time of day will again be displayed.
• a user wishes to delete a particular selection, he initiates the edit mode as described above, selects the day in which the selection is made by hitting the appropriate digit key and steps down, by sequentially hitting the digit key corresponding to the day he has selected, to either the time or channel number of the selection he wishes to delete.
• the up key which is also labelled CE (Clear Entry).
• CE CerEnt
• control portion 100 of microcomputer 34 controls the processing of binary signals stored in RAM 130 and the transfer of these binary signals between RAM 130 and digital tuner 14, volume control unit 22, on/off switching unit 28, display 40 and keyboard 32 through input/ output ports 140 under the control of a set of instructions stored in ROM 120.
• Control portion 100 of microcomputer 34 includes a main control logic unit 101, arithmetic and logic unit (ALU) 105, accumulator (ACC) 107, a power on clear unit 103 and an interrupt control unit 109.
• Main control logic unit 101 decodes binary signals representing an operation code of the instruction to be executed coupled to it through data bus 200 from ROM 120 and generates the necessary binary control signals to cause the appropriate portions of microcomputer 34 to perform the instruction.
• a power on clear unit 103 causes the binary signals representing the first instruction stored in ROM 120 to be coupled to main control logic unit 101 and causes various other portions of microcomputer 34 to be initialized for proper future operation when power is applied to microcomputer 34.
• ALU 105 receives binary control signals from main control logic unit 101 and performs the required arithmetic or logic operation.
• ACC 107 is the principal register of microcomputer 34 for the manipulation of data represented by binary signals. ACC 107 serves as one input of binary signals for ALU 105.
• the binary signals representing the result of an arithmetic or logical operation in ALU 105 are stored in ACC 107.
• Interrupt unit 109 is responsive to external interrupt pulses to generate binary signals representing the address of a predetermined external interrupt memory locationn f ROM 120.
• main control unit 101 causes instructions, beginning with th instructions stored in the predetermined external interrupt location, to be executed.
• the external interrupt pulse is derived from the 60 Hz line voltage by means of an amplifier 44. Since amplifier 44 is not coupled to power plug 26 through on/off switching unit 28, external interrupt pulses are coupled to external interrupt unit 109 even when the main portion of the receiver included in chassis 12 is off.
• Interrupt unit 109 is also responsive to internal interrupt pulses to generate binary signals representing the address of a predetermined internal interrupt memory location of ROM 120.
• main control unit 101 causes instructions, beginning with the instruction stored in the predetermined internal interrupt memory location, to be executed.
• the internal interrupt pulses are provided by a timer 111 which comprises a counter which is programmable in accordance with instructions stored in ROM 120 to divide the frequency of a clock signal, generated by a clock oscillator 113, by controllable factors.
• Clock oscillator 113 also provides the timing pulse utilized by various portions of microcomputer 34.
• the frequency of oscillation, e.g., 4 MHz, of clock oscillator 113 is determined by an externally connected timing network shown as a crystal 46.
• ROM 120 includes a predetermined number, e.g., 204 of memory locations or "bytes". Each memory location contains a predetermined number, e.g., 8, of memory cells or "bits". Each memory cell of a memory location permanently stores a binary signal.
• the binary signals stored in a memoy location of ROM 120 represent in combination an instruction to be executed by microcomputer 34.
• the memory locations of ROM 1 each have an address represented by binary signals generated by a ROM address register (ROMAR) unit 121.
• a data counter (DC) 122 associated with ROMAR 121, causes binary signals representing successive addresses to be generated.
• RAM 130 includes a predetermined number, e.g., 64, of memory locations or "bytes" each of which contains a predetermined number of memory cells or "bits", e.g., 8. Each memory cell of a memory location temporarily stores a binary signal. Since RAM 130 stores binary signals temporarily, it may be referred to as a "scratch pad" memory. Each memory location of RAM 130 has an address. Under the control of main control logic unit 101, an indirect scratch pad address register (ISAR) 131 generates binary signals representing the addresses of the memory locations of RAM 130.
• ISR indirect scratch pad address register
• RAM 130 The organization of RAM 130 is shown in FIGURE 4.
• Each of the 64 bytes of RAM 130 is identified by the hexidecimal code for the corresponding binary signals representing its address.
• Each of the 20 bytes, H'00 - H'13 (the symbol H' meaning hexidecimal representation), are also identified by a functional name corresponding to the function for which it is primarily intended.
• the remaining 44 bytes, H'14 through H'3F are utilized for the storage of information pertaining to future selections (i.e., future times and. channel numbers of channels to be tuned at those future times) and are so identified.
• each bit of the memory locations is identified with a number between 1 and 8, 8 being the most significant bit and 1 being the least significant bit.
• RAM location DAT is primarily utilized to store binary signals representing, in hexidecimal format, the key which was last operated.
• RAM location CHAN is utilized to store the binary signals representing the channel number presently being tuned. Only 7 binary signals representing the channel number are stored in CHAN to match the 7 bit format utilized in the RAM locations H'14 through H'3F and RAM location TEM2 where bit 8 is utilized to represent information pertaining to whether a future time is on the hour or half hour. Specifically, if the channel number is between 2 and 79, the 3 least significant bits of the binary signals representing the tens digit of the channel number in BCD (Binary Coded Decimal) format are stored in bits 7-5 of CHAN and the 4 binary signals representing the units digit of the channel number in BCD format are stored in bits 4-1 of CHAN.
• BCD Binary Coded Decimal
• RAM location VCNT is utilized to store the binary signals, representing in straight binary format, the present volume level.
• bits 8-6 of RAM location are utilized to store the binary signals, representing in straight binary format, the present volume level.
• HR are utilized to store the binary signals, in straight binary format, representing a decimal digit between 1 and 7 corresponding to the present day.
• Bit 5 of HR is utilized to store a "0" if the tens digit of the present hour is 0 anda "1" if the tens digit of the present hour is 1.
• Bits 4-1 of HR are utilized to store the binary signals representing, in BCD format, the units digit of the present hour.
• Bits 7-1 of RAM location MIN are utilized to store the binary signals representing, in straight binary format, the number of minute elapsed since the last full half hour.
• Bit 8 of MIN is set equal to "0" on the hour and to "1" on the half hour.
• RAM location SEC is utilized to store binary signals representing in straight binary format, the present number of seconds from the last minute.
• RAM location HZR is utilized to store thebinary signals representing, in straight binary format, the number of cycles of 60 Hz line voltage which have occurred since the last second.
• binary signals representing the present day, hour and minute are temporarily stored in RAM locations TEM1 and TEM2 and rearranged to fit the format for the present day, hour and minute utilized in RAM locations HR and MIN before they are stored in HR and MIN.
• binary signals representing the future day and hour information are stored in RAM location TEM1 in the same format utilized in RAM location HR. Since the 8 digit key is the key associated with Monday through Friday selections and there are only 3 bits of TEM1 allocated for the storage of day information permitting only binary signals representing, in straight binary format, the digits between 0 and 7 to be stored, the selection of M-F causes binary signals representing, in straight binary format, the digit 0 to be stored in bits 8-6 of TEM1.
• bit 8 of TEM2 If the future time is on the hour, a "0" is stored in bit 8 of TEM2 and if the selection is on the half hour a "1" is stored in bit 8 of TEM2.
• binary signals representing the channel number are stored in bits 7-1 of TEM2 in the same format utilized in RAM location CHAN.
• the binary signals stored in TEM1 and TEM2 are transferred, in the same format, to a pair of the last 44 locations of RAM 130.
• the selections are entered in RAM locations H'14 through H'3F in increasing order of day and time of day, respectively.
• M-F selections (encoded as day 0) will be stored at the top of the selection list. So that individual day selections are given priority over M-F selec ⁇ tions, during the scheduler mode, the selection list is searched from the bottom of the list to the top, i.e., from H'3F to H'14, to locate a match between a present day and time of day and a future day and time of day.
• RAM locations TTIM and TTIM are utilized to store binary signals representing, in hexidecimal format, the predetermined times allowed for displaying a prompt symbol during the clock setting, programming, editing or deleting modes or for performing certain operations, such as waiting for a keyboard entry to be "debounced", i.e., become stabilized.
• RAM location KB is utilized to store binary signals representing information pertaining to whether a key of keyboard 32 has been depressed and code indicating whether or not keyboard entries may be immediately acted upon. Bit of KB, designated KD, is set to a "1" when a key is depressed. KD is set to a "0" when the key is released.
• Bits 3-1 of KB designated CODE store binary signals representing, in straight binary format, the decimal number 0 when a keyboard entry can be immediately acted on, the decimal number 2 when a keyboard entry cannot be immediately acted on because a debounce operation is taking place and cannot be interrupted by a new keyboard entry, or the decimal number 3 when a keyboard entry cannot be immediately acted on because a channel changing operation is taking place and cannot be interrupted by a new keyboard entry.
• each of the 8 bits is utilized to store a binary signal indicating whether or not a certain event in the operation of the receiver has occurred.
• the following is a table identifying the occurrences which cause bits of FLAG to be set to a binary "1".
• CHDS A channel is being displayed.
• ESS The time of a future selection is being displayed during the edit mode.
• EDT The receiver is in the edit mode.
• PR The receiver is in the programming mode.
• UP The clock setting, programming, editing or deleting mode have been initiated by hitting the up key.
• EOS The clock setting mode has been complete
• RAM locations JUMPH (also designated KU), JUMPL (also designated KL), DCU (also designated QU), DCL (also designated QL) are utilized to store binary signals representing the addresses of certain locations of ROM 120 during the clock setting and programming modes to indicate which instruction should be executed next.
• RAM location NEXT is utilized to store binary signals representing certain hexidecimal codes during the clock setting and programming modes to indicate which prompt symbol should be displayed next.
• RAM locations TMP0 and TMP1 are utilized to temporarily store binary signals while they are rearranged to fit the format utilized in other RAM locations in which they are eventually to be stored.
• Binary signals stored in RAM 130 and ACC 107 as a result of an arithmetic or logical operation controlled by ALU 105 are coupled to various portions of the receiver outside microcomputer 34 through, bidirectional input/output ports 0, 1, 4 and 5, generally designated as 140. Each port has 8 terminals designated 0 through 7.
• Each element of display 40 is illuminated when a binary "1" is caused to be developed at a respective terminal' of ports 0 , 1 , 4 or 5.
• Terminals P4-0 through P4-3 are also coupled to channel number register 36 to couple binary signals representing, in BCD format, the tens and units digit of the channel number of a channel to be tuned, in sequence, to channel number register 36.
• Terminal P5-5 is coupled to channel number register 36 to couple a channel number strobe pulse to channel number register 36 to cause binary signals representing each digit of the channel number of the channel to be tuned to be entered in channel number register 36.
• Terminal P5-5 is also coupled to on/off switching unit 28.
• On/off switching unit 28 includes a switching device and a low pass filter for generating a control signal for the switching device selected so that the conduction of the switching device is only changed in response to signals having relatively long durations and are not affected by the relatively short duration channel number strobe pulse.
• a "0" is caused to be developed at P5-5
• a "1” is caused to be developed at P5-5.
• the five binary signals generated by keyboard 32 are coupled to terminal P5-0 through P5-4.
• Binary signals coupled to terminals P5-0. through P5-3 from keyboard 32 represent, in the manner indicated in FIGURE 3, the specific key operated.
• the binary signal coupled to terminal P5-4 from keyboard 32 is a keyboard strobe signal generated when any key of keyboard 32 has caused the generation of all the binary signals necessary to identify it.
• Terminal P5-6 is coupled to filter 42.
• a pulse signal is caused to be developed at P5-6, the duration of which determines the level of the DC control signal developed by low pass filter 42 to control the volume level.
• Operating voltage, VCC, for microcomputer 34 is derived by a control power supply unit 48.
• the 60 Hz input voltage to power supply unit 48 is not coupled to plug 26 through on/off switch 28 so that as long as line plug 26 is plugged in, operating voltage is supplied to microcomputer 34
• the reset signal for power on clear unit 103 is generated by power supply unit 48 when VCC reaches a predetermined threshold.
• Operating voltage for drivers 38 and display 40 is also generated by control power supply unit 48 so that display 40 may be utilized to display the time during the normal mode and the various prompt symbols and data to be entered or already entered, during the clock setting, programming and editing modes when the receiver is off.
• Chassis 12 including CTC-91 color television chassis digital tuner 14, manufactured by RCA Corporation channel number register and described in "RCA Television 36, and volume control Service Data for the CTC-91 unit 22 and keyboard 32 Series", File 1978 C-3 published by RCA Corporation,
• FIGURES 6-29 the manner in which binary signals are transferred between various memory locations of RAM 130 and on/off switching unit 28, keyboard 32, channel number register 36, display 40 and filter 42 to control the receiver during its various modes in accordance with instructions stored in ROM
• Rectangle an instruction or set of instructions Rectangle the binary signals stored in Y are surrounding X Y transferred to X
• FIGURE 6 indicates the relationship between the various flow charts shown in FIGURES 7-29.
• the description of each flow chart shown in FIGURES 7-29 is separately identified.
• a listing is included in the Appendix which indicates the instructions stored in ROM 120 for each portion of the flow charts when the present "scheduler" is implemented utilizing a Mostek 3870 microcomputer. The individual instructions are explained in the aforementioned "Mostek Single Chip Microcomputer MK3870" data book.
• each part of the flow charts shown in FIGURES 7-29 is identified by a hexidecimal number which corresponds to the first instruction in the listing for accomplishing that portion of the flow chart.
• the receiver proper is turned off (000B)
• display 40 is caused to display *- -: - - (001E) to indicate that the clock has not been set
• timer 111 is set to divide the frequency of the clock signal by 100,000 (0029) so that the internal interrupt signal hasa frequency of 40 Hz for the purpose of the CLOCK sequence to be described below.
• the KEYBOARD sequence determines whether the operation of a key of keyboard 32 should be responded to or whether it should not be responded to because some other operation requiring a predetermined time before completion is occurring.
• interrupt unit 109 is disabled from responding to an external or internal interrupt pulse so that the contents of RAM location TTIM, which are normally changed during a CLOCK sequence, are not changed while certain evaluations are made.
• an evaluation (00EB) is made to determine whether or not the binary signals stored in the CODE portion of RAM register FLAG represent 0, indicating that the present operation may be interrupted in response to a keyboard entry.
• the LI and INTl sequences are initiated during various other sequences and in turn cause the KEYBOARD sequence to be initiated.
• the keyboard is repeatedly examined to determine if there has been an entry.
• the binary signals representing the predetermined time delay allowed for a prompt symbol to be displayed, a keyboard entry to stabilize or a portion of the CHANNEL CHANGE sequence to be performed, initially stored in TTIM are transferred to TTIM (START) (00CA) so that the contents of TTIM (START) may be used to extend the time remaining for debouncing a keyboard entry if a user continues to hold down a key as previously describe (with reference to step 0108 of the KEYBOARD sequence).
• the bit KD of RAM location KEYBOARD is also set to a "1" (00CD) to indicate that the operation associated with a key previously hit has not been completed.
• the Ll sequence of operation is followed by the INTl sequence of operation in which interrupt enable unit 109 is enabled to respond to interrupt signals (00D1) and a determination is made whether the receiver proper is on or off (00D2) prior to initiating a VOLUME OUTPUT sequence.
• interrupt enable unit 109 is enabled to respond to interrupt signals (00D1) and a determination is made whether the receiver proper is on or off (00D2) prior to initiating a VOLUME OUTPUT sequence.
• the binary signals stored in DAT are examined to determine whether the up key has been hit (0130). If the up key has been hit, a determination is made whether the EDT bit of RAM location FLAG has been set to a "1" (0136). If EDT is set to a "1", it indicates that the editing mode has already been initiated and the user has hit the up key to delete a selection. Accordingly, an EDIT sequence is initiated which, in turn, results in the initiation of a DELETE sequence. If the up key has been hit, but EDT is not set to "1", the binary signals stored in RAM location FLAG are examined to determine if the bits CS or PR have been setto "1" (0134).
• CS or PR have been set to "1"
• CS or PR have not been set to "1” and if the receiver is off (013D), it indicates that the user wishes to start either the clock setting, programming or editing modes. In either case, certain RAM locations are cleared and a dash is displayed (0144 and 014D) in preparation for the next keyboard entry. Thereafter the Ll sequence is initiated to await the next entry. The Ll sequence is also initiated if the up key was hit and the receiver was on (013D). In the latter case, the volume level will be caused to increase, but the mode of operation will not be changed.
• a sequence of tests (0237, 023 0232, 0242, 0246, 0255) is performed to determine which of the clock setting, programming or editing modes have already been started or are to be started or whether the channel is to be changed if the receiver is off (01A4) and the user has not hit the down key (01AE); or if the receiver is on (01A4) and the user has thus far only made a "half entry", i.e., has thus far only hit a digit key corresponding to the tens digit of a channel number (01A8); or if the receiver is on (01A4) and the user has thus far not hit any digit key (01A8) and has not hit a digit key other than digit key 9 (01AB) to select a new channel.
• the UP, EOS, CS, PR and EDT bits of FLAG are examined to determine if the clock setting, programming or editing modes have already been started.
• the UP bit of FLAG is tested first. If UP has not been set to a "1", indicating that the user has not initiated the clock setting, programming or editing mode by hitting the up key when the receiver was off, a CHANGE routine is initiated as a preliminary to executing a channel change. Thereafter, the remaining ones of the EOS, CS, PR and EDT bits are then tested.
• the binary signals stored in DAT corresponding to the last key hit are then examined to determine if any one of the clock setting, programming or editing modes is to be initiated.
• a CHANNEL/CLOCK EXCHANGE sequence is initiated to enter thepresent time information into RAM 130. If the receiver is on (01A4) and the user has in the past made a "full entry" of a channel number to select a channel (01A8) and the key he has hit is the 9 digit key, the CHANNEL/CLOCK EXCHANGE sequence is initiated to exchange the channel and time display.
• the CHANNEL/CLOCK EXCHANGE sequence indicated in FIGURE 10, has the primary function of controlling when the channel number of a presently tuned channel or the present time is displayed.
• the ESS, EDT, CS, PR, UP and EOS bits of FLAG are examined (01BF) to determine if one of the clock setting, programming or editing scheduling modes has been initiated. If one of these bits is a "1" and CS and EOS are not both set to "1" (01DA) indicating that the user has terminated one of the clock setting, programming or editing modes before completing the sequence by hitting the up key, the present time is displayed if the clock has been set , or * - -: - - is displayed if the clock has not been set (01ED, 01F0, 01CF, 01D2, 01D6, 001E).
• the address of RAM location CHAN is stored in ISAR 131 (01CB)
• the address of RAM location MIN is stored in ISAR 131 (01D6).
• the CHANNEL/CLOCK EXCHANGE routine is also initiate at the end of a SEARCH routine through a sequence designated L80 to update the display of the present time.
• L80 the contents of FLAG are examined (01B9) to determine if one of the clock setting, programming or editing modes have been initiated. If so, the INTl routine is initiated to await the next keyboard entry.
• the CKDS and EDTS sequences for displaying the present time of day information in the normal mode are indicated in FIGURE 11.
• the CKDS sequence is initiated during the CHANNEL/CLOCK EXCHANGE sequence.
• the EDTS sequence is initated during an EDIT sequence of the editing mode in which the times and channel numbers of selections are reviewed.
• the address of the RAM location containing minute information (MIN in the case of CHANNEL/ CLOCK EXCHANGE and one of RAM locations H'14 - H'3F containing 1 ⁇ 2 HR and channel information in the case of EDIT) is stored in ISAR 131.
• the 1 ⁇ 2 HR bit of the then addressed RAM location is examined to decode and display the minutes information in decimal format (0092, 0095, 0098, 0099, 009A).
• decimal format 0092, 0095, 0098, 0099, 009A.
• bit 8 of the then addressed RAM location is processed to display minutes of the selection.
• the contents of the next RAM location are examined to decode and display the hours information in a 12 hour decimal format (00A7, 00A9, 00AD, 00.B0, 00B3, 00B4, 00B6, 00B7).
• CHDS The sequence CHDS, for displaying a channel number, is indicated in FIGURE 12. This routine is initiated during several other routines. During these routines, before the CHDS routine is initiated, binary signals are stored in ISAR to indicate the RAM location containing the binary signals which are to be processed to decode and display the channel number. During a CHANGE and the CHANNEL/CLOCK EXCHANGE sequences, the contents of ISAR 131 are set equal to the address of CHAN. During EDIT and SEARCH sequences, the contents of ISAR 131 are set equal to the address of one of the RAM locations H'14 through H'3F containing channel number information then being processed.
• the CHDS bit of FLAG is set to a "1" to indicate that the CHDS routine is in progress and the display is blanked or cleared of previous information (01F9, 01FC).
• "half entry” tests are conducted to determine if only the tens digit of the channel number has been entered (0203, 0205, 020A). If the contents of CHAN represent H'EE, it indicates that a "half entry” in which 8 is the tens digit has already been made. If the contents of CHAN represent ⁇ 'XE, where X is any hexidecimal number, it indicates that any other "half entry" has already been made.
• the function of the CHANGE sequence, indicated in FIGURE 13, is to encode and transfer binary signals stored in DAT generated in response to the operation of digit keys of keyboard 32 to CHAN.
• a "half entry" test is performed to determine whether the present number in CHAN is the tens or units digit of the channel number (0285). If the tens digit is being entered, it is encoded so as to indicate a "half entry" in which the tens digit is less than 8 (028D, 0290) or in which the tens digit is 8 (028D, 0293). If the first number being received is not less than or equal to 8, the Ll routine is initiated to wait for the entry of a proper digit (0289).
• the tens digit previously entered and the units digit now entered are encoded in the 7-bit format previously described and the results are stored in CHAN (0285, 0295, 0298, 029C, 029F, 02A2, 02A5).
• the contents of ISAR are set equal to the address of CHAN so that the new channel number may be displayed during the CHDS sequence as previously described.
• the CHCH sequence for changing a channel or turning the receiver on and off, is initiated when binary signals representing a new channel numb.er, including 00 to turn off the receiver, are stored in CHAN during the CHANGE sequence in response to either a manual channel selection by means of keyboard 32 or in response to the location of a RAM location between H'14 and H'3F containing the same time information as the present time during a SEARCH sequence.
• CHAN is examined to determine if only the tens digit of the channel number has been entered (050A) and, if so, Ll is initiated to await the entry of the units digit. Thereafter, if binary signals representing channel number 00 have been stored in CHAN (050E), the receiver is turned off by causing a "0" to be coupled through terminal P5-5 to on/off power switching unit 28 (0516). Thereafter, CKDS routine is initiated to display the present time (02AA) If CHAN contains a binary signal representing a channel number other than 00, the 7 binary signals representing the channel number stored in CHAN are decoded to form 8 binary signals representing the channel number and the results are stored in TMP1 (0511, 0513, 0514).
• the receiver is turned on by causing a "1" to be developed at terminal P5-5. Thereafter, a delay of 0.1 second is initiated by storing binary signals representing H'B8 in RAM location TTIM (0521, 0526, 0528, 053A).
• the KEYBOARD sequence initiates a WAT1 sequence in which the binary signals stored in TMP1 representing the tens digit of the channel number are coupled through terminals P4-0 through P4-3 to channel number register 36 and then a WAT2 sequence in which a channel number strobe signal is coupled through terminal P5-5 to channel number register 36 after a 10 milliseconddelay (0530, 0531, 0533, 0536, 0538, 0540, 0542) to enter binary signals representing the tens digit of the channel number in channel number register 36. Thereafter, the same two sequences are repeated to enter binary signals representing the units digit of the channel number.
• RAM location TEM1 Since the same two sequences are utilized for each digit of the channel number, the contents of RAM location TEM1 are utilized to indicate whether the units digit of the channel number has already been entered in channel number register 36 (052D, 0547, 054A). Since port 4 is coupled to the left-most digit of display 40 as well as channel number register 36, after the channel number is entered in channel number register 36, binary signals P4-0-7 are all set equal to "0" (0545) to blank the left-most digit of display 40. After the units binary signals representing the units digit have been entered in channel number register 36, Ll is initiated to await the next operation. CLOCK SET UP
• the MODE SELECT sequence initiates a CLOCK SET UP sequence, indicated in FIGURE 15.
• the CLOCK SET UP sequence causes binary signals representing the prompt symbol CS to be coupled to display 40 through ports 0 and 1. Since the dash in the right-most position of display 40 has already been caused to be displayed during the MODE SELECT sequence (014D), the symbol CS- is formed. Thereafter, bit CS of FLAG is set to a "1".
• Routine L15 is utilized in the same manner during the CLOCK SET and PROGRAM sequences to initiate the sequence for the various portions of these routines in order, e.g., to cause the units digit of the hour to be entered after the tens digit of the hour, to cause the tens digit of the minute to be entered after the units digit of the present hour, etc.
• PROGRAM SET UP If the up key has been hit (0237) and then any digit key is hit except the 9 digit key (0255), the MODE SELECT sequence initiates a PROGRAM SET UP sequence. Since the purpose of the programming mode is to enter information concerning future selections into a pair of RAM locations between H'14 and H'3F, the contents of each of the RAM locations H'14 through H'3F are compared to H'FF, H'FF representing an absence of stored information (026A, 026D, 0276). If there is no empty RAM location between H'14 and H'3F, the word "Full" is displayed (026F).
• CLOCK SET The CLOCK SET sequence consists of a series of sequences, SDAY, SHTN, SHTU, SMTN, SMTU, SPAM for setting the digit for the present day, the tens digit of the present hour, the units digit of the present hour, the tens digit of the present minute, the units digit of the present minute and AM or PM information, respectively.
• the function of the INST (INsert and STore) sequence, indicated in FIGURE 23, is to store the binary signals stored in TEM1 after the completion of the PROGRAM sequence representing the day and hour of the future selection and the binary signals stored in TEM2 representing the 1 ⁇ 2 hour and a channel number of the future selection into two respective RAM locations (the combination hereinafter being referred to as a slot) between H'14 and H'3F.
• the INST routine starts with a series of tests which determine whether the binary signals stored in RAM location H'14 represent H'FF, thereby indicating it is empty (049B, 049D), represent a day and hour which is the same as the day and hour represented by the binary signals stored in TEM1 (04A8), or represent a day and hour earlier than the day and hour represented by the binary signals stored in TEM1 (04AE). If none of these tests are successful, the contents of ISAR 131 are sequentially increased by 2 (04B0), because day and hour information is stored in every other RAM location between H'14 and H'3F starting with H'14, and the tests are repeated until one of the above-described tests is successful.
• the first empty slot is located (04D2, 04D5, 04DB) and the information presently stored in the list is moved down one slot at a time from the empty slot until the slot associated with the address previously saved in DAT is located (04DE, 04E3, 04E5, 04E8, 04EA, 04ED, 04EF, 04F2, 04F5, 04F8).
• the contents of TEM1 and TEM2 are stored in the slot associated with the address previously saved in DAT (04FC, 04FE).
• next RAM location which contain day and time of day information of the next selection
• the binary signals stored therein represent the same day and hour as the day and hour represented by the binary signals stored in TEM1 (04C4, 04C7). If this is so, it indicates that a slot has been found which contains the same day, hour and half hour information as that stored in TEM1 and TEM2 and the contents of this slot is replaced with the contents of TEM1 and TEM2 (04FC, 04FD, 04FE). Otherwise, the slot associated with the presently addressed RAM location contains binary signals representing a day and/or hour later than the day and/or hour represented by the binary signals stored in TEM1.
• the position of the slot is saved, the list is moved down slot by slot to the first empty location and the contents of TEM1 and TEM2 are entered into the slot having the saved address as indicated above. This result also occurs if it was initially determined (04AE) that the new entry was earlier than the time information pertaining to the day and hour stored in a presently addressed RAM location. Before the INST sequence is terminated, the PR and
• EOS bits of FLAG are set to a "0" (0502) and binary signals representing a delay of approximately 1 second are stored in TTIM so that the next prompt symbol (Pr-) is displayed approximately 1 second after the last entry, i.e., units digit of the channel number.
• the MODE SELECT sequence initiates the EDIT SET UP mode (0255).
• the EDT bit of FLAG is set to a "1" (0259) to indicate the user has initiated the editing mode.
• binary signals representing H'43 are stored in TEM2 (025C), H'43 being a code indicating that the first selection of a particular day is to be examined.
• the prompt symbol Ed- is displayed (025E) to indicate to a user that he should hit the digit key corresponding to the day he wishes examined.
• EDT sequence is initiated (0242).
• TEM2 is utilized as a temporary storage location for the address of the RAM location between H'14 and H'3F being examined.
• a test is conducted to determine if ISAR contains binary signals representing H'43 (02B7). If the editing mode has just been initiated, TEM2 will contain binary signals representing H'43 (since they were stored there during EDIT SET UP) indicating that the first selection in the particular day to be reviewed is to be examined.
• ISAR contains binary signals not representing H'43, it indicates that another selection in the same day is to be reviewed.
• TEM2 contains binary signals representing H'43
• the contents of DAT representing the number of the day to be reviewed are stored in TEM1 (02BD).
• RAM locations H'14 through H'3F are searched from the top to find the first RAM location with the signals representing the same day as that represented by the binary signals stored in TEM1 (02C0, 02D6, 02DB, 02DE, 02EF). If no match is found, EDIT SET UP is initiated and thereby Edis again displayed.
• the future time is displayed by initiating the EDTS sequence of CKDS utilized to display time (02E2, 02E5), ESS is set to a "1" (02E7) so that the channel number of the selection for which the match was found will be displayed next, and binary signals representing apporixmately a 1 second delay are stored in TTIM (02EA) so that the future time will be displayed for approximately 1 second before the corresponding channel number is displayed. Finally, the binary signals representing the RAM location of the selection just reviewed are stored in TEM2 (02EB) for the purpose of displaying the channel number of the selection.
• a DIS2 sequence also indicated in FIGURE 24, is initiated.
• the channel number of the selection just located will be displayed by initiating the CHDS sequence for displaying channel numbers, ESS is set to "0" so that the next display will be of time, and the symbol C is also displayed to indicate the channel number of the selection is being displayed (02F3, 02F5, 02F9, 02FB).
• the RAM location in which the future time of the next selection of the same day is stored in TEM2 (02FE, 0301).
• a test is made to determine if binary signals representing a code H'DD have. been stored in NEXT (030A).
• the code H'DD indicates that a selection has been deleted and the next selection after that in the same day is to be displayed or is being displayed. Accordingly, if the contents of NEXT represent H'DD, Ll is initiated to cause, by way of the PROMPT sequence, the display of the next selection in the same day, as will be described below, or to await the next keyboard entry.
• NEXT does not contain H'DD
• the prompt symbol "out” is displayed (030D)
• binary signals representing H'DD are stored in NEXT (0313)
• binary signals representing a time delay of approximately 1.5 seconds are stored in TTIM (0315) . This serves to establish the delay for displaying the "out" prompt symbol and before which a subsequent deletion can be made and thereby inhibits a user from accidentally making a deletion by mistake by operating too quickly.
• the binary signals representing the address of the RAM location corresponding to the time of the selection to be deleted are stored in TEM2 (0317, 031A, 031E) since the deletion command may have occurred while the channel number was being displayed and a final check is made to make sure that the RAM location containing the time of the selection to be deleted has been properly located (0320).
• the selections in RAM locations H'14 through H'3F are moved up two at a time (0328, 032B, 032D, 0330) so that the deletion in the selection list is made without having any empty slots. At this point, each selection has been moved up from its previous slot. However, because selections are written over the ones they replace, the last selection in the list appears twice.
• the PROMPT sequence is primarily utilized in conjunction with the RETURN sequence to determine which prompt symbol, if any, is to be displayed. It is recalled that during the CLOCK SET and PROGRAM sequences, binary signals representing the address of the ROM location containing the first instruction of the next sequence are stored in DC 122. During the following RETURN sequence, binary signals representing a code associated with the contents of DC 122 representing the next sequence of CLOCK SET or PROGRAM are stored in RAM location NEXT. In addition, during other sequences, such as EDIT, binary signals representing other codes are also stored in NEXT. The various codes stored in NEXT and their meanings are indicated below:
• H'7C SHTN is the next sequence.
• H'10 PHTN is the next sequence.
• H'C2 SPAM is the next sequence.
• H'D8 AMPM is the next sequence.
• H'DE The last digit of the present time has been entered.
• H'EE The last entry for a particular selection has been entered during PROGRAM.
• H'DD A selection has been deleted during DELETE and the next selection in the same day is to be displayed.
• NEXT represent H'DE (0189)
• binary signals representing H'00 are stored in NEXT and CHANNEL/CLOCK EXCHANGE sequence is initiated (at L75) to display the clock.
• code is H'DD (015F)
• TEM1 which contain binary signals representing the previously entered day, are stored in DAT (0160). This causes the next selection after a deleted selection in the day being reviewed to be displayed during EDIT.
• RAM location FLAG is also examined to determine if the bit ESS has been set to "1" (0168). If it has, it indicates that the future time of the selection being presently reviewed has been displayed and since the delay for the prompt symbol has expired (0156), the channel number of the selection being presently reviewed is caused to be displayed during EDIT.
• a series of tests (0166, 0175, 0178, 017A, 017C, 017E, 0180, 0183) are performed to determine which prompt symbol to display.
• the asterisk (*) is made to flash on and off. If NEXT contains binary signals representing either H'DE or H'C2 (017E, 0180), the input/output terminal associated with the asterisk display, P4-7, is examined to determine if it is a "1" (0183). If it is not, it is set to "1" (0186). If it is, it is set to a "0" (018A).
• the CLOCK sequence updates the contents of RAM locations HZR, SEC, MIN, HR and TTIM.
• the CLOCK routine is not initiated by any other routine. Rather, it is initiated in response to each external interrupt pulse generated by amplifier 44 in response to each cycle of the 60 Hz line voltage or, in the absence of the 60 Hz line voltage, in response to each internal interrupt pulse generated at a frequency of 40 Hz by the timer 111 in response to the 4 MHz clock output signal of clock 113.
• the contents of DC 122 are set to ROM address 00A0 and as a result the contents stored in RAM locations TTIM and HZR are each increased by 2 (0066, 0068). Thereafter, bit 8 of HZR is set to a "1".
• the 60 Hz external interrupt signal will not be generated and bit 8 of HZR will not be set to a "1".
• the 40 Hz internal interrupt signal will continue to be generated and, as a result, each cycle of the 40 Hz internal interrupt signal causes the contents of DC 122 to be set to ROM address 0020. Accordingly, since bit 8 of HZR is not set to a "1", the contents of HZR and TTIM are caused to be increased by 3 (0035, 0036, 0037).
• the contents of HZR will represent 120, i.e., 1 second.
• the contents of SEC are increased by 1 (005C, 006D).
• the contents of MIN and HOUR are updated at the proper time intervals, e.g., when there are 60 seconds (006F), 30 minutes (007D), 1 hour (0084) and 7 days (008B).
• the SEARCH sequence is initiated at minute intervals.
• the VOLUME sequence is initiated during the CLOCK sequence when the contents of SEC represent 120 (0057).
• the binary signals stored in RAM location VCNT are increased by 1 if the user has hit the up key (0040, 0049) and decreased by 1 if the user has hit the down key (0050, 0052). So that the volume is changed at a 30 Hz rate, contents of VCNT are only changed when bit 3 of HZR is a "1" (003D) since this bit changes to a "1" at a frequency of 30 Hz.
• VOLUME OUT During the VOLUME OUT sequence, indicated in
• FIGURE 7 the contents of VCNT are compared to the contents of timer 111. If the contents of VCNT represent a number greater than the contents represented by the contents of timer 111, a "1" is caused to be developed at terminal P5-6 (00D5, 00DD). Otherwise, a "0" is caused to be developed at P5-6 (00DD). As a result, the signal P5-6 has a pulse width which represents the volume level.
• the selections in the list between RAM locations H'14 and H'3F are examined to determine if there is a selection which has the same day and time of day as the present time. If so, binary signals representing the corresponding channel number are coupled to CHAN.
• the SEARCH sequence is initiated each minute on the minute, at the beginning of the SEARCH sequence the contents of SEC are set to represent 0 seconds (055B). If the clock has not been set, which would make the SEARCH sequence meaningless, the CKDS sequence is initiated (via L80 ) so that the symbol * - -: - - is displayed to indicate to a user that the clock has not been set (055D).
• each location of the selection list corresponding to day and hour information starting with location H'3E at the bottom of the list is examined until a match of day and hour and half hour is found or until the list has been completely searched (0562, 0565, 0566, 0568, 0569, 056C, 056E, 0571, 0572, 0577, 057C, 0582).
• the binary signals representing the present day and the binary signals representing the hour of the selection being examined are stored in ACC 107 (0565, 0566, 0568, 0569, 056C, 056E) and otherwise, the binary signals representing the day and hour of the selection are stored in ACC 107 (0571).
• the future half hour information of the selection is compared with the present half hour information stored in MIN (0582) until a match is found or the list is exhausted. If a complete match between the present time and the time of a selection is located, the binary signals representing the channel number of the selection are coupled to CHAN (0589), the channel number is displayed (058C, 058D) and the CHANNEL CHANGE sequence is initiated.

Landscapes

• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Circuits Of Receivers In General (AREA)
• Electric Clocks (AREA)
• Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Applications Claiming Priority (4)

Publications (1)

Family

ID=26264494

Family Applications (1)

Country Status (6)

Families Citing this family (5)

Family Cites Families (5)

• 1978
  • 1978-10-02 GB GB8023933A patent/GB2076242B/en not_active Expired
  • 1978-10-02 JP JP50001378A patent/JPS6352514B2/ja not_active Expired
  • 1978-10-02 WO PCT/US1978/000094 patent/WO1979000169A1/en unknown
  • 1978-10-02 DE DE19782857653 patent/DE2857653A1/de active Granted
• 1979
  • 1979-04-09 EP EP19780900133 patent/EP0007943A1/en not_active Withdrawn
• 1980
  • 1980-07-11 FR FR8015867A patent/FR2457618A1/fr active Granted

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events