EP0000317A1 - Method for providing a silicide electrode on a substrate such as a semiconductor substrate - Google Patents
Method for providing a silicide electrode on a substrate such as a semiconductor substrate Download PDFInfo
- Publication number
- EP0000317A1 EP0000317A1 EP78430003A EP78430003A EP0000317A1 EP 0000317 A1 EP0000317 A1 EP 0000317A1 EP 78430003 A EP78430003 A EP 78430003A EP 78430003 A EP78430003 A EP 78430003A EP 0000317 A1 EP0000317 A1 EP 0000317A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- silicide
- substrate
- silicon
- metal
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 51
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title description 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 29
- 239000010703 silicon Substances 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 238000001704 evaporation Methods 0.000 claims abstract description 14
- 230000008020 evaporation Effects 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 8
- 239000011733 molybdenum Substances 0.000 claims abstract description 8
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 8
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000010937 tungsten Substances 0.000 claims abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 229910052703 rhodium Inorganic materials 0.000 claims abstract description 5
- 239000010948 rhodium Substances 0.000 claims abstract description 5
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 24
- 238000007254 oxidation reaction Methods 0.000 claims description 24
- 238000000151 deposition Methods 0.000 claims description 9
- 238000010894 electron beam technology Methods 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 26
- 230000008569 process Effects 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 230000008021 deposition Effects 0.000 abstract description 5
- 239000002131 composite material Substances 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 239000000463 material Substances 0.000 description 16
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- 238000005554 pickling Methods 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 6
- 238000005507 spraying Methods 0.000 description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 239000012808 vapor phase Substances 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910008938 W—Si Inorganic materials 0.000 description 1
- TWRSDLOICOIGRH-UHFFFAOYSA-N [Si].[Si].[Hf] Chemical compound [Si].[Si].[Hf] TWRSDLOICOIGRH-UHFFFAOYSA-N 0.000 description 1
- 230000001464 adherent effect Effects 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- PDKHNCYLMVRIFV-UHFFFAOYSA-H molybdenum;hexachloride Chemical compound [Cl-].[Cl-].[Cl-].[Cl-].[Cl-].[Cl-].[Mo] PDKHNCYLMVRIFV-UHFFFAOYSA-H 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 235000021110 pickles Nutrition 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/14—Schottky barrier contacts
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/147—Silicides
Definitions
- the present invention relates to a method for depositing a silicide such as a molybdenum, tantalum, rhodium or tungsten silicide on a substrate, and in particular on a semiconductor substrate constituted by doped silicon or by doped polycrystalline silicon.
- a silicide such as a molybdenum, tantalum, rhodium or tungsten silicide
- Polycrystalline silicon has been widely used for several years as an interconnection material in integrated circuits. The use of this type of silicon is desirable because it is very stable at high temperature and lends itself to chemical vapor deposition of silicon dioxide, or to its thermal growth. Polycrystalline silicon interconnections have been used in various types of integrated circuits, notably in sets of charge coupled devices, in logic sets and in sets of memory cells with a single field effect device.
- polycrystalline silicon has the drawback of offering a relatively high electrical resistance.
- the attempts which have been made so far to improve the performance of certain integrated circuits by reducing the dimensions of the devices have not been successful since the voltage drops which occur in the interconnections do not decrease when- the voltage levels required for the operation of the circuits are reduced. It would therefore be desirable to reduce the layer (or sheet) resistance of the polycrystalline silicon interconnections in order to increase the speed of the circuit.
- hafnium silicide obtained by depositing hafnium on polycrystalline silicon, then by heating the assembly to react the .hafnium and the polycrystalline silicon.
- the same article also suggests the use for this purpose of tantalum, tungsten or molybdenum silicides; the strips can then be covered with chemically deposited oxide in the vapor phase.
- the spraying techniques proposed have a certain number of drawbacks. In particular, it is difficult to vary the composition of silicide precisely. On the other hand, when using spraying techniques, it is necessary to carry out a pickling to remove the metal from certain regions where no silicide must be formed.
- One of the objects of the present invention is therefore to provide a process making it possible to produce silicides of certain refractory metals which makes it possible to control and vary precisely the composition of the silicide thus produced.
- Another object of the invention is to provide a method making it possible to remove the silicide from certain desired parts of the substrate using simple pickling techniques using the use of a solvent, without there being any need to use more complex pickling techniques that require masking.
- the present invention makes it possible to form a layer of a silicide on a substrate, the metal used being able to be molybdenum, tantalum, tungsten, rhodium or combinations of these materials.
- the metal silicide is obtained by depositing, by simultaneous evaporation, the silicon and one of said metals on the desired substrate, then subjecting the assembly. â heat treatment.
- silicon dioxide can be obtained from the silicide layer by thermal oxidation of the latter at high temperature.
- silicides in the mass that is to say in the volume, does not allow us to assume that it would be possible by thermal oxidation of the oxide layers of sufficient thickness to be able be used in integrated circuits.
- molybdenum silicide and tungsten silicide when they form a mass or a volume are known for their excellent resistance to oxidation.
- FIGS. 1A and 1B schematically represent different stages of the production of integrated circuits by means of the method of the present invention.
- FIGS. 2A to 2C schematically represent the steps of another embodiment of an integrated circuit by means of the method of the present invention.
- FIGS. 3A and 4A illustrate the relationship which exists between the temperature and the oxidation time, on the one hand, and the thickness of an oxide layer obtained in the cases of WSi 2 and. At MOSi 2 respectively, on the other hand.
- FIGS. 3B and 4B illustrate the relationship which exists between the oxidation time and the temperature, on the one hand, and the layer resistance in the case of WSi 2 and MOSi 2 respectively, on the other hand.
- the process of the present invention can be used to form films of the desired silicide on any substrate capable of withstanding the high temperatures used during the deposition process by simultaneous evaporation and sufficiently adherent to said silicide.
- the present method can advantageously be used for the purposes of producing integrated circuits and, therefore, is of particular interest when the substrate is made of silicon or of polycrystalline silicon.
- the present process lends itself particularly well to the production of layers intended to cover door electrodes made of doped polycrystalline silicon, to the replacement of polycrystalline silicon as the material constituting such electrodes, and finally to the formation of covering layers. directly broadcast bands in doped silicon.
- the metal silicides to which the present invention is addressed are molybdenum silicide and / or tantalum silicide and / or tungsten silicide and / or rhodium silicide.
- the preferred metals to constitute these silicides include molybdenum, tantalum and tungsten, and more particularly still the latter.
- metallic silicides comprise approximately 60 to 25% by atomic weight of the metal.
- the metal and the silicon are vaporized under a high vacuum and deposited simultaneously on the substrate.
- the vacuum used is of the order of 10 -5 to 10 -7 torr.
- the metal and the silicon are heated under a high vacuum and brought to a temperature sufficient to cause them to evaporate.
- An electron beam evaporator is preferably used for this purpose and an electron beam gun for silicon and another gun for metal is preferably used due to the fact that the evaporation of these materials occurs at speeds different.
- the use of said evaporator requires the use, as a heat source, of heat which is dissipated when a highly collimated electron beam strikes the material.
- the evaporation of the metal and of the silicon should take place at the rate of approximately 25 to 50 Angstroms per second.
- the substrate which it is desired to cover is generally maintained at a temperature between ambient temperature and approximately 400 ° C., and preferably between 150 ° C. and approximately 250 ° C. during the deposition of the metal and the silicon.
- the substrate is removed from the device used for the purpose of evaporation under vacuum, then heated in an inert atmosphere at temperatures varying between 700 ° C and 1100 ° C approximately and preferably between 900 ° C and 1100 ° C.
- Suitable inert atmospheres in which the heat treatment can be carried out include argon, helium and hydrogen.
- the inert atmosphere must not contain water vapor, oxygen, carbon compounds, nitrogen or other substances which could cause the formation of carbide, oxide or nitride during the treatment. thermal.
- the substrate is heated to the above temperatures for a period of time sufficient to cause a reaction of the metal and the silicon deposited thereon so as to form the desired silicide.
- This time interval generally varies between 15 minutes and 2 hours approximately, and it is inversely dependent on the temperature used.
- the substrate covered with the silicide layer may optionally be subject to oxidation so as to cover said layer of self-passivation oxide. It was found that the decrease in the conductivity of the silicide layer which resulted from the oxidation was much less than that which theoretically should have resulted from the oxidation of a determined part of the layer. For example, 50% oxidation of the layer does not cause a corresponding decrease of 50% in its conductivity. This result would be due to a preferential oxidation of the silicon contained in the silicide layer and to a backscattering of the metal, thus causing the formation of a metal-enriched silicide layer below the oxidized layer. In this regard, we will usefully refer to the article by J. Berkowitz-Matluck et al, entitled "High Temperature Oxidation II. Molybdenum Silicide” published in the publication "J. Electrochemical Soc ..” Vol. 112, No. 6, page 583, June 1965.
- FIGS. 3B and 4B show the variations in the resistivity of certain oxidized silicides according to the temperatures.
- the overall results indicate that an improvement of about 30% in the conductivity is obtained compared to the theoretical conductivity corresponding to the oxidized percentage of the layer.
- the oxidation of molybdenum silicide at 1000 ° C for more than 15 minutes had a detrimental effect on the layer and modified its properties. Such conditions should therefore be avoided in the case of molybdenum silicide so that its conductivity remains high.
- the oxidation was carried out in the vapor phase under the conditions specified.
- the preferred oxidation process is wet oxidation (water vapor) or dry-wet-dry oxidation. This process makes it possible to obtain better results in terms of breakdown than the other techniques. Oxidation in the vapor phase should preferably be carried out at temperatures varying between 800 ° C and 1100 ° C approximately at a pressure roughly corresponding to atmospheric pressure. The duration of the oxidation depends on the thickness of the oxide layer which it is desired to obtain and generally varies between 15 minutes and 2 hours approximately. For example, obtaining a thickness close to or greater than 1,000 Angstroms requires more than 2 hours at approximately 800 ° C and approximately 30 minutes at approximately 950 ° C.
- Figures 3A and 4A show the growth of the insulating oxide on the silicide during exposure to steam at temperatures and during the time intervals indicated.
- Table I in the appendix indicates the measured values of the resistance of silicide film produced in accordance with the present invention by evaporation by means of an electron beam.
- the films deposited on the silicon substrate were about 0.5 micron thick.
- Table II in the appendix shows the improved conductivity of the silicide produced in accordance with the method of the present invention compared to that of doped silicon. This improved conductivity plays an important role in increasing the speed of transmission of signals on a transmission line.
- Table III in the appendix shows that the use of metallic silicide carried out in accordance polvcristalin, taking into account the tensor of flat justifye and of the tensile of electrucye click in the case where the oxide covers the silicide.
- the movable click field in the case of a self-oxidized silicide with a thickness of approximately 3,000 Anqstroms disposed between an aluminum conductor and the layer of silicide was greater than 2 to 3 mV am.
- the present invention can also be applied to a substrate made of a material other than silicon.
- the expressions “metallic type interconnection strip” and “high conductivity interconnection strip” used below relate to strips of a metal such as aluminum as well as to non-metallic materials which may nevertheless have comparable conductivity.
- references made below to impurities of a "first type” and a “second type” mean for example that, if the "first type” is p, the “second type” is n, and vice versa.
- FIG. 1A shows part of a p-type silicon substrate 1 having a desired crystal orientation (for example ⁇ 100>) and produced by cutting and polishing a p-type silicon ball or bar (c (i.e. in the presence of a p-type dopant such as boron) in accordance with conventional techniques.
- a p-type dopant such as boron
- Other p-type dopants usable with silicon are aluminum, gallium and indium.
- a door insulator consisting of a thin layer of silicon dioxide 2 is then grown or deposited.
- This layer the thickness of which is generally between 200 and 1000 Angstroms, is preferably formed by thermal oxidation of the surface of silicon at 1000 ° C in the presence of dry oxygen.
- a polycrystalline silicon shell 3 was deposited.
- This layer generally has a thickness varying between 500 and 2000 Angstroms enviror. and can be carried out by chemical vapor deposition.
- This layer is then doped using an n-type dopant such as arsenic, phosphorus or antimony, using a conventional technique.
- this layer can be doped with phosphorus using the technique which consists in depositing a layer of POCl 3 and heating it to approximately 1000 ° C. so as to introduce the phosphorus into layer 3, which then becomes of the type not.
- the residue is then removed from the layer of POCl 3 by pickling the pellet in buffered hydrofluoric acid.
- a silicide layer 4 with a thickness of about 2000 to 4000 Angstroms is then formed on the layer 3 using the method of the present invention and described above.
- a door configuration can be carried out using any known technique for lithography, for example chemical pickling, pickling in a plasma, pickling with reactive ions, etc.
- the techniques which can be used for this purpose vary in their details, but all make it possible to obtain a composite layer, polycrystalline silicon silicide, having a determined configuration.
- hot H 3 PO made it possible to selectively pickle the cicides with respect to polycrystalline silicon or SiO 2 .
- the silicruros must preferably be pickled using a so-called "dry” technique such as the technique of pickling with reactive ions using empioi of a material such as CF 4 .
- n-type source and drain regions are then formed using well-known ion implantation or diffusion techniques.
- source and drain regions 7 and 8 of type n, respectively, of a depth of 2,000 Angstroms can be produced by implantation of As 75 using an energy of approximately 100 KeV and a dose of 4 x 1 0 15 atoms / cm2.
- the polycrystalline silicon layer 3 and the silicide layer 4 act as a mask and prevent n-type impurities from entering the region of the FET channel which is located below layer 3.
- the boundaries between the n-type source and drain regions and therefore the FET channel are determined by the dimensions of the polycrystalline silicon gate. This technique is generally called “self-aligned door” technique.
- a self-formed passivation silicon dioxide layer 5 is then formed in situ over the door regions using the previously described oxidation techniques. For example, the whole is subjected to an oxidation in the vapor phase at approximately 950 ° C. for approximately 30 minutes to obtain an oxide thickness also greater than 1,000 and 3,000 Angstroms, which depends well on the metal chosen as we 'saw above.
- silicon dioxide about 1,000 to 1,500 Angstroms thick to prevent any interaction between the silicide layer and a metallic interconnection, for example, of aluminum, which would be subsequently applied.
- the oxide layers and the metallic layers are defined using conventional masking and pickling techniques. For example, silicon dioxide can be removed using buffered hydrofluoric acid and aluminum can be stripped using a mixture of phosphoric acid and nitric acid. Aluminum can be deposited by spraying or by evaporation.
- FIGS. 2A to 2C illustrate another use of the present invention for the purpose of manufacturing integrated circuits.
- the following technique is particularly advantageous because it offers the possibility of removing the deposited silicide from predetermined regions of the substrate, using lift-off techniques.
- the substrate 11 is covered with a layer of a material 13 which makes it possible to obtain a suitable configuration for the separation step.
- the material constituting the layer 13 is a resistant material sensitive to radiation in which the desired configuration is generated by conventional techniques (for example by means of a PMMA type resist electron with a masking device. electron beam).
- layer 13 could consist of several layers of sensitive materials, so as to obtain the desired release geometry in the case of materials only capable of withstanding temperatures. moderately high treatments.
- the substrate is doped in the regions which are not protected by the mask so as to form n-type regions 12, for example source and drain regions of a FET.
- Techniques. such as ion implantation of As, P or Sb can be used for the purpose of doping this region.
- a layer 14 of metal and silicon is deposited on the substrate by means of the simultaneous evaporation step previously described.
- the layer 14 is not continuous, that is to say that there are no connections between the regions which are above the mask and those which are not, as would occur in the case of the use of a spraying technique, because the latter would cause an overlap of the edges which could cause such a connection or interconnection.
- the material constituting the mask and that which covers it can therefore be easily removed by means of a simple release technique using a solvent such as acetone which removes the resistant material which remained to form said mask.
- the assembly is then subjected to a heat treatment at temperatures varying between 700 and 1,100 ° C. approximately in an inert atmosphere such as argon, hydrogen or helium, as required by the present invention, to form the silicide.
- the silicide layer 14 can then be oxidized so as to be covered a passivation oxide layer.
- a composite mask 15 such as a layer of silicon nitride deposited on top of a layer of silicon dioxide, is disposed above the channel region of the FET device, in order to serve as a mask preventing or blocking any oxidation substrate at this location.
- Doping impurities 16 such as boron atoms can be introduced using ion implantation techniques into the field regions.
- a layer 17 of silicon dioxide is then grown, for example, by chemical vapor deposition, on the parts of the substrate which are not protected by the mask 15.
- the composite oxidation blocking mask is then removed using an appropriate solvent. If, for example, silicon nitride is used, it can be pickled in a phosphoric acid solution at 180 ° C. The silicon dioxide can be pickled in a buffered hydrofluoric acid solution.
- a silicon dioxide door insulator 18 is then grown on the substrate.
- the doping of the channel region if necessary, is carried out by ion implantation.
- This material can be obtained by simultaneous evaporation and heating of the silicon and metal, by deposition of polycrystalline silicon alone, or by deposition of polycrystalline silicon and a layer formed by simultaneous evaporation and heating of the silicon and metal in accordance with the techniques of the present invention.
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Abstract
- Le procédé de la présente invention est principalement caractérisé en ce qu'il prévoit la dépôt simultané de métal et de silicium sur le substrat par évaporation et le chauffage du substrat pour former le siliciure. Le métal peut être choisi dans le groupe comprenant le tungstène, le molybdène, le tantale et le rhodium. Dans un transistor à effet de champ (FET), le procédé peut contribuer à la formation d'une électrode de composite de porte par exemple une couche de siliciure 4 et une couche de silicium polycristallin 3; la couche de siliciure peut être aisément oxydée sans pour autant nuire à sa conductivité. Le présent procédé trouve en particulier application dans la fabrication des réseaux de mémoire à un seul FET.- The process of the present invention is mainly characterized in that it provides for the simultaneous deposition of metal and silicon on the substrate by evaporation and the heating of the substrate to form the silicide. The metal can be chosen from the group comprising tungsten, molybdenum, tantalum and rhodium. In a field effect transistor (FET), the method can contribute to the formation of a gate composite electrode, for example a layer of silicide 4 and a layer of polycrystalline silicon 3; the silicide layer can be easily oxidized without affecting its conductivity. The present method finds particular application in the manufacture of memory networks with a single FET.
Description
La présente invention concerne un procédé permettant de déposer un siliciure tel qu'un siliciure de molybdène, de tantale, de rhodium ou de tungstène sur un substrat, et notamment sur un substrat semiconducteur constitué par du silicium dopé ou par du silicium polycristallin dopé.The present invention relates to a method for depositing a silicide such as a molybdenum, tantalum, rhodium or tungsten silicide on a substrate, and in particular on a semiconductor substrate constituted by doped silicon or by doped polycrystalline silicon.
Le silicium polycristallin est très utilisé depuis quelques années comme matériau d'interconnexion dans les circuits intégrés. L'emploi de ce type de silicium est souhaitable car il est très stable à température élevée et se prête au dépôt chimique en phase vapeur du dioxyde de silicium, ou à sa croissance thermique. Des interconnexions en silicium polycristallin ont été utilisées dans divers types de circuits intégrés, notamment dans des ensembles de dispositifs à couplage de charges, dans des ensembles logiques et dans des ensembles de cellules de mémoire à un seul dispositif à effet de champ.Polycrystalline silicon has been widely used for several years as an interconnection material in integrated circuits. The use of this type of silicon is desirable because it is very stable at high temperature and lends itself to chemical vapor deposition of silicon dioxide, or to its thermal growth. Polycrystalline silicon interconnections have been used in various types of integrated circuits, notably in sets of charge coupled devices, in logic sets and in sets of memory cells with a single field effect device.
En revanche, le silicium polycristallin présente l'inconvénient d'offir une résistance électrique relativement élevée. Les tentatives qui ont été faites jusqu'à présent pour améliorer la performance de certains circuits intégrés en réduisant les dimensions des dispositifs, n'ont pas été couronnées de succès car les chutes de tension qui se produisent dans les interconnexions ne diminuent pas lorsqu'- on diminue les niveaux de tension requis aux fins du fonctionnement des circuits. Il serait donc souhaitable de réduire la résistance de couche (ou de feuille) des interconnexions en silicium polycristallin afin d'augmenter la vitesse du circuit.On the other hand, polycrystalline silicon has the drawback of offering a relatively high electrical resistance. The attempts which have been made so far to improve the performance of certain integrated circuits by reducing the dimensions of the devices have not been successful since the voltage drops which occur in the interconnections do not decrease when- the voltage levels required for the operation of the circuits are reduced. It would therefore be desirable to reduce the layer (or sheet) resistance of the polycrystalline silicon interconnections in order to increase the speed of the circuit.
On a proposé de remplacer le silicium polycristallin par divers métaux réfractaires tels que le molybdène et le tungstène. Toutefois, ces métaux s'oxydent lors du dépôt chimique en phase vapeur du dioxyde de silicium, et comme ces oxydes sont beaucoup moins stables que le dioxyde de silicium, il posent un problème de fiabilité du circuit intégré finalement. Afin de résoudre le problème que pose l'utilisation de tels métaux réfractaires utilisés seuls, on a proposé de remplacer une partie de la couche de silicium polycristallin par une couche d'un siliciure de certains métaux. Par exemple, l'article de Rideout intitulé "Reducing the Sheet Resistance of Polysilicon Lines in Integrated Circuits" paru dans la publication "IBM Techni- cal Disclosure Bulletin", Volume 17, N°6, Novembre 1974, pages 18311833, suggère l'emploi d'un siliciure de hafnium obtenu en déposant du hafnium sur du silicium polycristallin, puis en chauffant l'ensemble pour faire réagir le .hafnium et le silicium polycristallin. Le même article suggère également l'emploi à cette fin des siliciures de tantale, de tungstène ou de molybdène; les bandes pouvant ensuite être recouvertes d'oxyde déposé chimiquement en phase vapeur.It has been proposed to replace polycrystalline silicon with various refractory metals such as molybdenum and tungsten. However, these metals oxidize during the chemical vapor deposition of silicon dioxide, and since these oxides are much less stable than silicon dioxide, they ultimately pose a problem of reliability of the integrated circuit. In order to solve the problem posed by the use of such refractory metals used alone, it has been proposed to replace part of the layer of polycrystalline silicon with a layer of a silicide of certain metals. For example, Rideout's article entitled "Reducing the Sheet Resistance of Polysilicon Lines in Integrated Circuits" published in the publication "IBM Technical Disclosure Bulletin",
Par ailleurs, un procédé connu (brevet des E.U.A. N°3381182 et analogue à celui qui vient d'être mentionné permet de procéder au dépôt chimique en phase vapeur d'un siliciure de molybdène sur du silicium polycristallin par la réduction, d'un mélange de chlorure de molybdène et de silane, par de l'hydrogène. D'autres procédés permettant de réaliser divers siliciures et notamment un siliciure de tungstène en pulvérisant du tungstène sur un substrat contenant du silicium, puis en chauffant l'ensemble pour provoquer la formation du siliciure, sont décrits dans le brevet français N° 2.250.193 et dans l'article de V. Kumar intitulé "Fabrication and Thermal Stability de W-Si Ohmic Contacts" paru dans la publication "Journal of the Electrochemical Society, Solid-State Science and Technology", Février 1975, pages 262 à 269.Furthermore, a known process (US Patent No. 3381182 and analogous to that which has just been mentioned makes it possible to proceed with the chemical vapor deposition of a molybdenum silicide on polycrystalline silicon by the reduction, of a mixture of molybdenum chloride and silane, with hydrogen. Other processes making it possible to produce various silicides and in particular a tungsten silicide by spraying tungsten on a substrate containing silicon, then by heating the assembly to cause the formation of silicide, are described in French patent No. 2,250,193 and in the article by V. Kumar entitled "Fabrication and Thermal Stability of W-Si Ohmic Contacts" published in the publication "Journal of the Electrochemical Society, Solid-State Science and Technolo g y ", February 1975, pages 262 to 269.
Toutefois, les techniques de pulvérisation proposées présentent un certain nombre d'inconvénients. En particulier, il est difficile de faire varier avec précision la composition de siliciure. D'autre part, lors de l'emploi de techniques de pulvérisation, il est nécessaire de procéder à un décapage pour retirer le métal de certaines régions où on ne doit pas former de siliciure.However, the spraying techniques proposed have a certain number of drawbacks. In particular, it is difficult to vary the composition of silicide precisely. On the other hand, when using spraying techniques, it is necessary to carry out a pickling to remove the metal from certain regions where no silicide must be formed.
L'un des objets de la présente invention est donc de fournir un procédé permettant de réaliser des siliciures de certains métaux réfractaires qui permette de commander et de faire varier avec précision la composition du siliciure ainsi-réalisé.One of the objects of the present invention is therefore to provide a process making it possible to produce silicides of certain refractory metals which makes it possible to control and vary precisely the composition of the silicide thus produced.
Un autre objet de l'invention est de fournir un procédé permettant de retirer le siliciure de certaines parties désirées du substrat en utilisant de simples techniques de décapage faisant appel à l'emploi d'un solvant, sans qu'il y ait lieu d'avoir recours à des techniques de décapage plus complexes qui nécessitent un masquage.Another object of the invention is to provide a method making it possible to remove the silicide from certain desired parts of the substrate using simple pickling techniques using the use of a solvent, without there being any need to use more complex pickling techniques that require masking.
La présente invention permet de former une couche d'un siliciure sur un substrat, le métal employé pouvant être du molybdène, du tantale, du tungstène, du rhodium ou des combinaisons de ces matériaux. Le siliciure métallique est obtenu en procédant au dépôt par évaporation simultanée du silicium et de l'un desdits métaux sur le substrat désiré, puis en soumettant l'ensemble. â un traitement thermique.The present invention makes it possible to form a layer of a silicide on a substrate, the metal used being able to be molybdenum, tantalum, tungsten, rhodium or combinations of these materials. The metal silicide is obtained by depositing, by simultaneous evaporation, the silicon and one of said metals on the desired substrate, then subjecting the assembly. â heat treatment.
Par ailleurs, du dioxyde de silicium peut être obtenu à partir de la couche de siliciure par oxydation thermique de celle-ci à température élevée. Ce que l'on sait des propriétés des siliciures dans la masse, c'est-à-dire dans le volume ne permet pas de supposer que l'on pourrait obtenir par oxydation thermique des couches d'oxyde d'une épaisseur suffisante pour pouvoir être employées dans des circuits intégrés. Par exemple, le siliciure de molybdène et le siliciure de tungstène quand ils constituent une masse ou un volume sont connus pour leur excellente résistance à l'oxydation. A cet égard, on se reportera utilement aux comptes-rendus de la "Fourth International Chemical Vapor Deposition Conference", publiés par l'Electrochemical Society", Princeton N.J.(U.S.A.) 1974 pour l'article de Lo et al. intitulé "A CVD Study of the Tungsten-Silicon System". On pourra également se reporter à l'ouvrage "Engineering Properties of Selected Ceramic Materials", paru dans la publication "The American Ceramic Society, Inc ...", Colombus Ohio (U.S.A.) 1966. En ce qui concerne notamment le di siliciure de molybdène, on a pu déterminer qu'une couche d'oxyde d'une épaisseur de 10 microns pourrait être obtenue en 60 minutes à 1.050°C en fonction de la quantité d'oxygène utilisée pour la formation du film. Une telle épaisseur conviendrait plus à des applications aérospatiales qu'à des applications aux circuits intégrés.Furthermore, silicon dioxide can be obtained from the silicide layer by thermal oxidation of the latter at high temperature. What we know about the properties of silicides in the mass, that is to say in the volume, does not allow us to assume that it would be possible by thermal oxidation of the oxide layers of sufficient thickness to be able be used in integrated circuits. For example, molybdenum silicide and tungsten silicide when they form a mass or a volume are known for their excellent resistance to oxidation. In this regard, we will usefully refer to the reports of the "Fourth International Chemical Vapor Deposition Conference", published by the Electrochemical Society ", Princeton NJ (USA) 1974 for the article by Lo et al. Entitled" A CVD Study o f the Tungsten-Silicon System ". Reference may also be made to the book" Engineering Properties of Selected Ceramic Materials ", published in the publication" The American Ceramic Society, Inc ... ", Colombus Ohio (USA) 1966 With regard in particular to molybdenum di silicide, it has been possible to determine that an oxide layer with a thickness of 10 microns could be obtained in 60 minutes at 1.050 ° C. depending on the quantity of oxygen used for film formation, such a thickness would be more suitable for aerospace applications than applications for integrated circuits.
D'autres objets, caractéristiques et avantages de la présente invention ressortiront mieux de l'exposé qui suit, fait en référence aux dessins annexés à ce texte, qui représentent un mode de réalisation préféré de celle-ci.Other objects, characteristics and advantages of the present invention will emerge more clearly from the following description, made with reference to the drawings appended to this text, which represent a preferred embodiment thereof.
Les figures 1A et 1B représentent schématiquement différentes étapes de la réalisation de circuits intégrés au moyen du procédé de la présente invention.FIGS. 1A and 1B schematically represent different stages of the production of integrated circuits by means of the method of the present invention.
Les figures 2A à 2C représentent schématiquement les étapes d'une autre réalisation d'un circuit intégré au moyen du procédé de la présente invention.FIGS. 2A to 2C schematically represent the steps of another embodiment of an integrated circuit by means of the method of the present invention.
Les figures 3A et 4A illustrent la relation qui existe entre la température et le temps d'oxydation, d'une part, et l'épaisseur d'une couche d'oxyde obtenue dans les cas du WSi2 et.au MOSi2 respectivement, d'autre part.FIGS. 3A and 4A illustrate the relationship which exists between the temperature and the oxidation time, on the one hand, and the thickness of an oxide layer obtained in the cases of WSi 2 and. At MOSi 2 respectively, on the other hand.
Les figures 3B et 4B illustrent la relation qui existe entre le temps d'oxydation et la température, d'une,_part, et la résistance de couche dans les cas du WSi2 et du MOSi2 respectivement, d'autre part.FIGS. 3B and 4B illustrate the relationship which exists between the oxidation time and the temperature, on the one hand, and the layer resistance in the case of WSi 2 and MOSi 2 respectively, on the other hand.
Le procédé de la présente invention peut être utilisé pour former des films du siliciure désiré sur n'importe quel substrat capable de résister aux températures élevées mises en oeuvre durant le procédé de dépôt par évaporation simultanée et suffisamment adhérent audit siliciure . Le présent procédé peut être avantageusement employé aux fins de.la réalisation de circuits intégrés et, de ce fait, présente un intérêt particulier lorsque le substrat est en silicium ou en silicium polycristallin. Par exemple, le présent procédé se prête particulièrement bien, à la réalisation de couches destinées à recouvrir des électrodes de porte en silicium polycristallin dopé, au remplacement du silicium polycristallin en tant que matériau constituant de telles électrodes, et enfin à la formation de couches recouvrant directement des bandes diffusées en silicium dopé.The process of the present invention can be used to form films of the desired silicide on any substrate capable of withstanding the high temperatures used during the deposition process by simultaneous evaporation and sufficiently adherent to said silicide. The present method can advantageously be used for the purposes of producing integrated circuits and, therefore, is of particular interest when the substrate is made of silicon or of polycrystalline silicon. For example, the present process lends itself particularly well to the production of layers intended to cover door electrodes made of doped polycrystalline silicon, to the replacement of polycrystalline silicon as the material constituting such electrodes, and finally to the formation of covering layers. directly broadcast bands in doped silicon.
Les siliciures métalliques auxquels s'adresse la présente invention sont le siliciure de molybdène et/ ou le siliciure de tantale et/ou le siliciure de tungstène et/ou le siliciure de rhodium. Les métaux préférés pour constituer ces siliciures comprennent le molybdène, le tantale et le tungstène, et plus particulièrement encore ce dernier. En général, les siliciures métalliques comportent approximativement de 60 à 25% en poids atomique du métal.The metal silicides to which the present invention is addressed are molybdenum silicide and / or tantalum silicide and / or tungsten silicide and / or rhodium silicide. The preferred metals to constitute these silicides include molybdenum, tantalum and tungsten, and more particularly still the latter. In general, metallic silicides comprise approximately 60 to 25% by atomic weight of the metal.
Selon la présente invention, le métal et le silicium sont vaporisés sous un vide poussé et déposés simultanément sur le substrat. Le vide employé est de l'ordre de 10-5 à 10-7 torr. Dans le procédé d'évaporation sous vide, le métal et le silicium sont chauffés sous un vide poussé et portés à une température suffisante pour provoquer leur évaporation. On utilise de préférence à cette fin un évaporateur à faisceau électronique et l'on utilise de préférence un canon à faisceau électronique pour le silicium et un autre canon pour le métal en raison du fait que l'évaporation de ces matériaux se produit à des vitesses différentes. L'emploi dudit évaporateur nécessite l'utilisation, comme source de chaleur, de la chaleur qui est dissipée lorsqu'un faisceau d'électrons fortement collimaté frappe le matériau. Les dispositifs et les techniques utilisés aux fins de l'évaporation du silicium et du métal sont bien connus et n'ont donc pas à être décrits ici de façon détaillée. De préférence, l'évaporation du métal et du silicium doit avoir lieu à raison de 25 à 50 Angstroms environ par seconde. Le substrat que l'on désire recouvrir est en général maintenu à une température comprise entre la température ambiante et 400°C environ, et de préférence entre 150°C et 250°C environ lors du dépôt du métal et du silicium.According to the present invention, the metal and the silicon are vaporized under a high vacuum and deposited simultaneously on the substrate. The vacuum used is of the order of 10 -5 to 10 -7 torr. In the vacuum evaporation process, the metal and the silicon are heated under a high vacuum and brought to a temperature sufficient to cause them to evaporate. An electron beam evaporator is preferably used for this purpose and an electron beam gun for silicon and another gun for metal is preferably used due to the fact that the evaporation of these materials occurs at speeds different. The use of said evaporator requires the use, as a heat source, of heat which is dissipated when a highly collimated electron beam strikes the material. The devices and techniques used for the evaporation of silicon and metal are well known and therefore need not be described here in detail. Preferably, the evaporation of the metal and of the silicon should take place at the rate of approximately 25 to 50 Angstroms per second. The substrate which it is desired to cover is generally maintained at a temperature between ambient temperature and approximately 400 ° C., and preferably between 150 ° C. and approximately 250 ° C. during the deposition of the metal and the silicon.
Une fois que la quantité désirée de métal et de silicium a été déposée sur le substrat, ce dernier est retiré de l'appareil utilisé aux fins de l'évaporation sous vide, puis chauffé dans une atmosphère inerte à des températures variant entre 700°C et 1100°C environ et de préférence entre 900°C et 1100°C. La température maximum convenable est essentiellement fonction de considérations pratiques et, en particulier, est choisie de=manière à éviter une formation excessive de grains dans la couche de siliciure. Les atmosphères inertes convenables dans lesquelles le traitement thermique peut être effectué comprennent l'argon, l'hélium et l'hydrogène.Once the desired amount of metal and silicon has been deposited on the substrate, the substrate is removed from the device used for the purpose of evaporation under vacuum, then heated in an inert atmosphere at temperatures varying between 700 ° C and 1100 ° C approximately and preferably between 900 ° C and 1100 ° C. The suitable maximum temperature is essentially a function of practical considerations and, in particular, is chosen to = avoid excessive grain formation in the silicide layer. Suitable inert atmospheres in which the heat treatment can be carried out include argon, helium and hydrogen.
L'atmosphère inerte ne doit pas comporter de vapeur d'eau, d'oxygène, de composés à base de carbone, d'azote ou d'autres substances qui pourraient provoquer la formation de carbure, d'oxyde ou de nitrure pendant le traitement thermique.The inert atmosphere must not contain water vapor, oxygen, carbon compounds, nitrogen or other substances which could cause the formation of carbide, oxide or nitride during the treatment. thermal.
Le substrat est chauffé aux températures ci-dessus pendant un intervalle de temps suffisant pour provoquer une réaction du métal et du silicium déposé sur celui-ci de manière à former le siliciure désiré. Cet intervalle de temps varie généralement entre 15 minutes et 2 heures environ, et il est inversement fonction de la température utilisée.The substrate is heated to the above temperatures for a period of time sufficient to cause a reaction of the metal and the silicon deposited thereon so as to form the desired silicide. This time interval generally varies between 15 minutes and 2 hours approximately, and it is inversely dependent on the temperature used.
Après le traitement thermique, le substrat racouvert de la couche de siliciure peut éventuellement faire l'objet d'une oxydation de manière à recouvrir ladite couche d'oxyde d'auto-passivation. On a constaté que la diminution de la conductivité de la couche de siliciure qui résultait de l'oxydation était très inférieure à celle qui aurait dû théoriquement résulter de l'oxydation d'une partie déterminée de la couche. Par exemple, une oxydation de 50% de la couche n'entraîne pas une diminution correspondante de 50% de sa conductivité. Ce résultat serait dû à une oxydation préférentielle du silicium contenu dans la couche de siliciure et à une rétro- diffusion du métal, provoquant ainsi la formation d'une couche de siliciure enrichie en métal au-des- sous de la couche oxydée. A cet égard, on se reportera utilement à l'article de J. Berkowitz-Matluck et al, intitulé "High Temperature Oxidation II. Molybdenum Silicide" paru dans la publication "J. Electrochemical Soc.." Vol. 112, N° 6, page 583, Juin 1965.After the heat treatment, the substrate covered with the silicide layer may optionally be subject to oxidation so as to cover said layer of self-passivation oxide. It was found that the decrease in the conductivity of the silicide layer which resulted from the oxidation was much less than that which theoretically should have resulted from the oxidation of a determined part of the layer. For example, 50% oxidation of the layer does not cause a corresponding decrease of 50% in its conductivity. This result would be due to a preferential oxidation of the silicon contained in the silicide layer and to a backscattering of the metal, thus causing the formation of a metal-enriched silicide layer below the oxidized layer. In this regard, we will usefully refer to the article by J. Berkowitz-Matluck et al, entitled "High Temperature Oxidation II. Molybdenum Silicide" published in the publication "J. Electrochemical Soc .." Vol. 112, No. 6, page 583, June 1965.
Les figures 3B et 4B montrent les variations de la résistivité de certains siliciures oxydés selon les températures. Les résultats d'ensemble indiquent qu'une amélioration de 30% environ de la conductivité est obtenue par rapport à la conductivité théorique correspondant au pourcentage oxydé de la couche. L'oxydation du siliciure de molybdène à 1000°C pendant plus de 15 minutes a eu un effet nuisible sur la couche et modifié les propriétés de celle-ci. Il conviendrait donc d'éviter de telles conditions dans le cas du siliciure de molybdène afin que sa conductivité reste élevée. L'oxydation a été effectuée en phase vapeur dans les conditions spécifiées.FIGS. 3B and 4B show the variations in the resistivity of certain oxidized silicides according to the temperatures. The overall results indicate that an improvement of about 30% in the conductivity is obtained compared to the theoretical conductivity corresponding to the oxidized percentage of the layer. The oxidation of molybdenum silicide at 1000 ° C for more than 15 minutes had a detrimental effect on the layer and modified its properties. Such conditions should therefore be avoided in the case of molybdenum silicide so that its conductivity remains high. The oxidation was carried out in the vapor phase under the conditions specified.
Le procédé préféré d'oxydation est une oxydation humide (vapeur d'eau) ou une oxydation sèche-humide- sèche. Ce procédé permet en effet d'obtenir des meilleurs résultats en termes de claquage que les autres techniques. L'oxydation en phase vapeur doit de préférence être effectuée à des températures variant entre 800°C et 1100°C environ à une pression correspondant à peu près à la pression atmosphérique. La durée de l'oxydation est fonction de l'épaisseur de la couche d'oxyde que l'on désire obtenir et varie généralement entre 15 minutes et 2 heures environ. Par exemple, l'obtention d'une épaisseur voisine ou supérieure à 1.000 Angstroms nécessite plus de.2 heures à environ 800°C et 30 minutes environ à 950°C environ.The preferred oxidation process is wet oxidation (water vapor) or dry-wet-dry oxidation. This process makes it possible to obtain better results in terms of breakdown than the other techniques. Oxidation in the vapor phase should preferably be carried out at temperatures varying between 800 ° C and 1100 ° C approximately at a pressure roughly corresponding to atmospheric pressure. The duration of the oxidation depends on the thickness of the oxide layer which it is desired to obtain and generally varies between 15 minutes and 2 hours approximately. For example, obtaining a thickness close to or greater than 1,000 Angstroms requires more than 2 hours at approximately 800 ° C and approximately 30 minutes at approximately 950 ° C.
Les figures 3A et 4A montrent la croissance de l'oxyde isolant sur le siliciure pendant l'exposition à la vapeur aux températures et pendant les intervalles de les temps indiqués.Figures 3A and 4A show the growth of the insulating oxide on the silicide during exposure to steam at temperatures and during the time intervals indicated.
Le tableau I en annexe indique les valeurs mesurées de la résistance de film de siliciure réalisé conformément à la présente invention par évaporation au moyen d'un faisceau électronique. Les films déposés sur le substrat de silicium avaient une épaisseur d'environ 0,5 micron.Table I in the appendix indicates the measured values of the resistance of silicide film produced in accordance with the present invention by evaporation by means of an electron beam. The films deposited on the silicon substrate were about 0.5 micron thick.
Le tableau II en annexe permet de constater la conductivité améliorée du siliciure réalisé conformément au moyen du procédé de la présente invention comparée à celle du silicium dopé. Cette meilleure conductivité joue un rôle important en ce qui concerne l'augmentation de la vitesse de transmission des signaux sur une ligne de transmission.Table II in the appendix shows the improved conductivity of the silicide produced in accordance with the method of the present invention compared to that of doped silicon. This improved conductivity plays an important role in increasing the speed of transmission of signals on a transmission line.
Le tableau III en annexe montre que l'emploi du siliciure métallique réalisé conformément
Par ailleurs, on a constate que le champ de claquaqe moven dans le cas d'un silicture auto-oxzdé d'une épaisseur d'environ 3.000 Anqstroms disposé entre un conducteur d'.aluminium st la couche de siliciure était supérieur a 2 à 3 mV am.
D'autre part, la présente invention peut s'appliquer également à un substrat constitué par un matériau autre que le silicium. Les expressions "bande d'interconnexion de type métallique" et "bande d'interconnexion de conductivité élevée" employées ci-après se rapportent à des bandes d'un métal tel que l'aluminium ainsi qu'à des matériaux non métalliques qui peuvent néanmoins présenter une conductivité comparable.On the other hand, the present invention can also be applied to a substrate made of a material other than silicon. The expressions “metallic type interconnection strip” and “high conductivity interconnection strip” used below relate to strips of a metal such as aluminum as well as to non-metallic materials which may nevertheless have comparable conductivity.
Les références .faites ci-après à des impuretés d'un "premier type" et d'un "second type" signifient par exemple que, si le "premier type" est p, le "second type" est n, et inversement.The references made below to impurities of a "first type" and a "second type" mean for example that, if the "first type" is p, the "second type" is n, and vice versa.
On a représenté sur la figure 1A une partie d'un substrat en silicium 1 de type p présentant une orientation cristalline désirée (par exemple <100>) et réalisé en découpant et en polissant une boule ou un barreau de silicium de type p (c'est-à-dire en présence d'un dopant du type p tel que le bore) conformément à des techniques classiques. D'autres dopants de type p utilisables avec le silicium sont l'aluminium, le gallium et l'indium.FIG. 1A shows part of a p-
On fait ensuite croître ou l'on dépose un isolant de porte constitué par une mince couche de dioxyde de silicium 2. Cette couche, dont l'épaisseur est généralement comprise entre 200 et 1000 Angstroms est de préférence formée par oxydation thermique de la surface de silicium à 1000°C en présence d'oxygène sec.A door insulator consisting of a thin layer of
On procéda ensuite au dépôt d'une ccuche de silicium polycristallin 3. Cette couche a généralement une épaisseur variant entre 500 et 2000 Angstroms enviror. et peut être réalisée par dépôt chimique en phase vapeur. On dope ensuite cette couche au moyen d'un dopant de type n tel que l'arsenic, le phosphore ou l'antimoine, en utilisant une technique classique. Par exemple, on peut doper cette couche avec du phosphore en utilisant la technique qui consiste à déposer une couche de POCℓ3 et en la chauffant à 1000°C environ de manière à introduire le phosphore dans la couche 3, qui devient, alors de type n. On retire ensuite le résidu de la couche de POCℓ3 en décapant la pastille dans de l'acide, fluorhydrique tamponné. Une couche de siliciure 4 d'une épaisseur d'environ 2000 à 4000 Angstroms est ensuite formée sur la couche 3 en utilisant le procédé de la présente invention et décrit ci-dessus.Next, a
Une configuration de porte peut étre réalisée en utilisant pour la lithcgrapnie une technique connue quelconque, par exemple le décapage chimique, le décapage dans un plasma, le décapage par ions réactifs, etc... Les techniques susceptibles d'être utilisées à cette fin varient dans leurs détails, mais permettent toutes d'obtenir une couche composite, siliciure silicium polycristallin, présentant une configuration déterminée. Dans le das d'un décapage chimirue, on a constaté que du H3PO, chaud permettait de décaper de façon sélective les ciliciures par rapport au silicium polycristallin ou au SiO2. Les silicruros doivent le préférenze stre décapés au moyen d'une technique dite "sèche" telie que la technique to décapage par ions réactifs faisant appel à l'empioi d'un matériau tel que le CF4.A door configuration can be carried out using any known technique for lithography, for example chemical pickling, pickling in a plasma, pickling with reactive ions, etc. The techniques which can be used for this purpose vary in their details, but all make it possible to obtain a composite layer, polycrystalline silicon silicide, having a determined configuration. In the das of a chemistry pickling, it was found that hot H 3 PO made it possible to selectively pickle the cicides with respect to polycrystalline silicon or SiO 2 . The silicruros must preferably be pickled using a so-called "dry" technique such as the technique of pickling with reactive ions using empioi of a material such as CF 4 .
Les régions de source et de drain de type n sont ensuite formées au moyen des techniques bien connues d'implantation ou de diffusion ionique. Par exemple, des régions de source et de drain 7 et 8 de type n, respectivement, d'une profondeur de 2.000 Angstroms peuvent être réalisées par implantation d'As75 en utilisant une énergie d'environ 100 KeV et une dose de 4 x 1015 atomes/cm2. Pendant l'implantation, la couche en silicium polycristallin 3 et la couche de siliciure 4 font fonction de masque et empêchent les impuretés de type n de pénétrer dans la région du canal du FET qui se trouve au-dessous de la couche 3.The n-type source and drain regions are then formed using well-known ion implantation or diffusion techniques. For example, source and
Les limites entre les régions de source et de drain de type n et donc le canal du FET sont déterminées par les dimensions de la porte en silicium polycristallin. Cette technique est généralement dite technique de "porte auto-alignée".The boundaries between the n-type source and drain regions and therefore the FET channel are determined by the dimensions of the polycrystalline silicon gate. This technique is generally called "self-aligned door" technique.
Une couche de dioxyde de silicium de passivation auto-formée 5 est ensuite formée in situ sur les régions de porte au moyen des techniques d'oxydation précédemment décrites. Par exemple, l'ensemble fait l'objet d'une oxydation en phase vapeur à 950°C environ pendant 30 minutes environ pour obtenir une épaisseur d'oxyde également supérieure à 1.000 et 3.000 Angstroms qui dépend bien sur du métal choisi comme on l'a vu ci-dessus.A self-formed passivation
On procède ensuite au dépôt chimique en phase vapeur d'une couche de. dioxyde de silicium d'une épaisseur d'environ 1.000 à.1.500 Angstroms pour prévenir toute inter-action entre la couche de siliciure et une interconnexion métallique, par exemple, en aluminium, qui serait ultérieurement appliquée. Les couches d'oxyde et les couches métalliques sont définies au moyen de techniques classiques de masquage et de décapage. Par exemple, le dioxyde de silicium peut être retiré en utilisant de l'acide fluorhydrique tamponné et l'aluminium peut être décapé au moyen d'un mélange d'acide phosphorique et d'acide nitrique. L'aluminium peut être déposé par pulvérisation ou par évaporation.One then proceeds to the chemical vapor deposition of a layer of. silicon dioxide about 1,000 to 1,500 Angstroms thick to prevent any interaction between the silicide layer and a metallic interconnection, for example, of aluminum, which would be subsequently applied. The oxide layers and the metallic layers are defined using conventional masking and pickling techniques. For example, silicon dioxide can be removed using buffered hydrofluoric acid and aluminum can be stripped using a mixture of phosphoric acid and nitric acid. Aluminum can be deposited by spraying or by evaporation.
Les figures 2A à 2C illustrent une autre utilisation de la présente invention aux fins de la fabrication de circuits intégrés. La technique ci-après est particulièrement avantageuse parce qu'elle offre la possibilité de retirer le siliciure déposé de régions prédéterminées du substrat, en utilisant des techniques d'élimination par décollement (lift off).FIGS. 2A to 2C illustrate another use of the present invention for the purpose of manufacturing integrated circuits. The following technique is particularly advantageous because it offers the possibility of removing the deposited silicide from predetermined regions of the substrate, using lift-off techniques.
Le substrat 11 est recouvert d'une couche d'un matériau 13 qui permet d'obtenir une configuration convenable en vue de l'étape de décollement. Dans le cas le plus simple, le matériau constituant la couche 13 est un matériau résistant sensible au rayonnement dans lequel la configuration désirée est engendrée au moyen de techniques classiques (par exemple au moyen d'un électron résist du type PMMA avec un appareil de masquage à faisceau électronique). On notera que la couche 13 pourrait être constituée par plusieurs couches de matériaux sensibles, de façon à obtenir la géométrie de décollement désirée dans le cas de matériaux seulement capables de résister à des températures de traitements modérément élevées.The
Une fois que la configuration désirée de la couche 13 a été obtenue, le substrat est dopé dans les régions qui ne sont pas protégées par le masque de manière à former régions 12 de type n par exemple des régions de source et de drain d'un FET . Des techniques. telles que l'implantation ionique d'As, de P ou de Sb peuvent être employées aux fins du dopage de cette région.Once the desired configuration of the
Une couche 14 de métal et de silicium est déposée sur le substrat au moyen de l'étape d'évaporation simultanée précédemment décrite. La couche 14 n'est pas continue, c'est-à-dire qu'il n'y a pas de liaisons entre les régions qui se trouvent au-dessus du masque et celles qui ne le sont pas, comme cela se produirait dans le cas de l'emploi d'une technique de pulvérisation, car cette dernière provoquerait un recouvrement des bords qui pourrait entraîner une telle liaison ou interconnexion. Le matériau constituant le masque et celui qui le recouvre peuvent donc être aisément retirés au moyen d'une simple technique de décollement en utilisant un solvant tel que l'acétone qui élimine le matériau résistant qui subsistait pour former ledit masque.A
L'ensemble est ensuite soumis à un traitement thermique à des températures variant entre 700 et 1.100°C environ dans une atmosphère inerte telle que de l'argon, de l'hydrogène ou de l'hélium, comme l'exige la présente invention, pour former le siliciure. La couche de siliciure 14 pourra ensuite être oxydée de manière à être recouverte d'une couche d'oxyde de passivation.The assembly is then subjected to a heat treatment at temperatures varying between 700 and 1,100 ° C. approximately in an inert atmosphere such as argon, hydrogen or helium, as required by the present invention, to form the silicide. The
Un masque composite 15 tel qu'une couche de nitrure de silicium déposée au-dessus d'une couche de dioxyde de silicium, est disposé au-dessus de la région de canal du dispositif FET, afin de servir comme masque empêchant ou bloquant toute oxydation du substrat à cet emplacement.A composite mask 15 such as a layer of silicon nitride deposited on top of a layer of silicon dioxide, is disposed above the channel region of the FET device, in order to serve as a mask preventing or blocking any oxidation substrate at this location.
Des impuretés de dopage 16 telles que des atomes de bore peuvent être introduites au moyen de techniques d'implantation ionique, dans les régions de champ. On fait croître ensuite une couche 17 de dioxyde de silicium, par exemple, par dépôt chimique en phase vapeur, sur les parties du substrat qui ne sont pas protégées par le masque 15.Doping
Le masque composite de blocage d'oxydation est ensuite retiré au moyen d'un solvant approprié. Si, par exemple, on utilise du nitrure de silicium, celui-ci peut être décapé dans une solution d'acide phosphorique à 180°C. Le dioxyde de silicium peut être décapé dans une solution d'acide fluorhydrique tamponné.The composite oxidation blocking mask is then removed using an appropriate solvent. If, for example, silicon nitride is used, it can be pickled in a phosphoric acid solution at 180 ° C. The silicon dioxide can be pickled in a buffered hydrofluoric acid solution.
On fait ensuite croître sur le substrat un isolant de porte en dioxyde de silicium 18. Le dopage de la région du canal, si nécessaire, est effectué par une implantation ionique. On procède ensuire au dépôt du matériau constituant la porte, puis à sa délimitation selon une configuration désirée au moyen des techniques connues de masquage et de décapage. Ce matériau peut être obtenu par évaporation simultanée et chauffage du silicium et du métal, par dépôt de silicium polycristallin seul, ou par dépôt du silicium polycristallin et d'une couche formée par évaporation simultanée et chauffage du silicium et du métal conformément aux techniques de la présente invention.A silicon
Bien que l'on ait décrit dans ce qui précède et représenté sur les dessins les caractéristiques essentielles de la présente invention appliquées à un mode de réalisation préféré de celle-ci, il est évident que l'homme de l'art peut y apporter toutes modifications de forme ou de détail qu'il juge utiles, sans pour autant sortir du cadre de ladite invention.
Claims (11)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US811914 | 1977-06-30 | ||
| US05/811,914 US4180596A (en) | 1977-06-30 | 1977-06-30 | Method for providing a metal silicide layer on a substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0000317A1 true EP0000317A1 (en) | 1979-01-10 |
| EP0000317B1 EP0000317B1 (en) | 1982-05-19 |
Family
ID=25207936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP78430003A Expired EP0000317B1 (en) | 1977-06-30 | 1978-06-22 | Method for providing a silicide electrode on a substrate such as a semiconductor substrate |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4180596A (en) |
| EP (1) | EP0000317B1 (en) |
| JP (1) | JPS5852342B2 (en) |
| CA (1) | CA1100648A (en) |
| DE (1) | DE2861841D1 (en) |
| IT (1) | IT1112638B (en) |
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Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0017697A1 (en) * | 1979-03-01 | 1980-10-29 | International Business Machines Corporation | Interconnection device for integrated semiconductor circuits, and process for its manufacture |
| FR2458900A1 (en) * | 1979-06-11 | 1981-01-02 | Gen Electric | CONDUCTIVE HETEROGENEOUS STRUCTURE FOR INTEGRATED CIRCUITS AND METHOD OF MANUFACTURE |
| EP0022474A1 (en) * | 1979-07-03 | 1981-01-21 | Siemens Aktiengesellschaft | Method for forming low-resistive diffusion regions in the silicon-gate-technology |
| EP0024905A2 (en) * | 1979-08-25 | 1981-03-11 | Zaidan Hojin Handotai Kenkyu Shinkokai | Insulated-gate field-effect transistor |
| EP0024905A3 (en) * | 1979-08-25 | 1982-01-27 | Zaidan Hojin Handotai Kenkyu Shinkokai | Insulated-gate field-effect transistor |
| FR2489591A1 (en) * | 1980-08-27 | 1982-03-05 | Philips Nv | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE |
| EP0090318A3 (en) * | 1982-03-30 | 1986-01-15 | Siemens Aktiengesellschaft | Process for manufacturing integrated circuits comprising mos field-effect transistors using silicon gate technology having silicide layers on diffusion regions as low-ohmic conductors |
| EP0090318A2 (en) * | 1982-03-30 | 1983-10-05 | Siemens Aktiengesellschaft | Process for manufacturing integrated circuits comprising MOS field-effect transistors using silicon gate technology having silicide layers on diffusion regions as low-ohmic conductors |
| EP0096773A2 (en) * | 1982-06-11 | 1983-12-28 | International Business Machines Corporation | Method of making high dielectric constant insulators and capacitors using same |
| EP0096773A3 (en) * | 1982-06-11 | 1984-02-22 | International Business Machines Corporation | Method of making high dielectric constant insulators and capacitors using same |
| EP0100454A1 (en) * | 1982-07-05 | 1984-02-15 | Kabushiki Kaisha Toshiba | Semiconductor device having a conductive layer consisting of a high-melting point metal silicide and a method for manufacturing such a semiconductor device |
| EP0132720A1 (en) * | 1983-07-20 | 1985-02-13 | Siemens Aktiengesellschaft | Integrated semiconductor circuit having an external aluminium or aluminium alloy contact interconnection layer |
| EP0207486A1 (en) * | 1985-07-02 | 1987-01-07 | Siemens Aktiengesellschaft | Integrated circuit containing MOS transistors and comprising a gate metallization of a metal or a metal silicide of the elements tantalum or niobium, as well as a method of producing this gate metallization |
| EP0219827A2 (en) * | 1985-10-25 | 1987-04-29 | International Business Machines Corporation | Improved process for forming low sheet resistance metal silicide layers on semiconductor substrates |
| EP0219827A3 (en) * | 1985-10-25 | 1989-01-11 | International Business Machines Corporation | Improved process for forming low sheet resistance metal silicide layers on semiconductor substrates |
| EP0224199A1 (en) * | 1985-11-27 | 1987-06-03 | Siemens Aktiengesellschaft | Method for producing highly integrated circuits of p- and n-channel MOS transistors with gate electrodes consisting of a double layer of polysilicon and metal silicide |
| EP0466166A1 (en) * | 1990-07-13 | 1992-01-15 | Kabushiki Kaisha Toshiba | Gate or interconnection for semiconductor device and method of manufacture thereof |
| US5256894A (en) * | 1990-07-13 | 1993-10-26 | Kabushiki Kaisha Toshiba | Semiconductor device having variable impurity concentration polysilicon layer |
Also Published As
| Publication number | Publication date |
|---|---|
| US4180596A (en) | 1979-12-25 |
| IT7824502A0 (en) | 1978-06-13 |
| JPS5852342B2 (en) | 1983-11-22 |
| EP0000317B1 (en) | 1982-05-19 |
| CA1100648A (en) | 1981-05-05 |
| JPS5413283A (en) | 1979-01-31 |
| DE2861841D1 (en) | 1982-07-08 |
| IT1112638B (en) | 1986-01-20 |
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