EA201700120A1 - COMPUTER SYSTEM - Google Patents

COMPUTER SYSTEM

Info

Publication number
EA201700120A1
EA201700120A1 EA201700120A EA201700120A EA201700120A1 EA 201700120 A1 EA201700120 A1 EA 201700120A1 EA 201700120 A EA201700120 A EA 201700120A EA 201700120 A EA201700120 A EA 201700120A EA 201700120 A1 EA201700120 A1 EA 201700120A1
Authority
EA
Eurasian Patent Office
Prior art keywords
microprocessor
rom
external
chip
address space
Prior art date
Application number
EA201700120A
Other languages
Russian (ru)
Other versions
EA038978B1 (en
Inventor
Павел Николаевич ОСИПЕНКО
Дмитрий Сергеевич КОРОЛЕВ
Константин КРАСИК
Константин Львович ГУРИН
Григорий Юрьевич ХРЕНОВ
Original Assignee
Открытое Акционерное Общество "Байкал Электроникс"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Открытое Акционерное Общество "Байкал Электроникс" filed Critical Открытое Акционерное Общество "Байкал Электроникс"
Publication of EA201700120A1 publication Critical patent/EA201700120A1/en
Publication of EA038978B1 publication Critical patent/EA038978B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Abstract

Изобретение относится к вычислительной технике. Технический результат заключается в оптимизации выполнения программы инициализации из внешнего последовательного ПЗУ путем отображения адресов данных, располагающихся во внешнем последовательном ПЗУ, в адресное пространство микропроцессора. Компьютерная система включает в себя систему на кристалле и внешнее последовательное ПЗУ, причем система на кристалле включает в себя микропроцессор, содержащий по меньшей мере одно микропроцессорное ядро; контроллер внешнего последовательного ПЗУ; устройство прямого отображения адресов данных, располагающихся во внешнем последовательном ПЗУ, в адресное пространство микропроцессора; по меньшей мере одно интерфейсное устройство; по меньшей мере одно устройство внутренней памяти и устройство внутренней коммутации, обеспечивающее взаимодействие между микропроцессором и остальными устройствами системы на кристалле; при этом устройство прямого отображения адресов данных, располагающихся во внешнем последовательном ПЗУ, в адресное пространство микропроцессора содержит регистр считанных данных, регистр адреса и конечный автомат устройства прямого отображения адресов.The invention relates to computing. The technical result consists in optimizing the execution of the initialization program from the external serial ROM by mapping data addresses located in the external serial ROM into the address space of the microprocessor. A computer system includes a system on a chip and an external serial ROM, and the system on a chip includes a microprocessor containing at least one microprocessor core; external serial controller; a device for direct mapping of data addresses located in an external sequential ROM into the address space of the microprocessor; at least one interface device; at least one internal memory device and an internal switching device providing interaction between the microprocessor and other devices of the system on a chip; the device for direct mapping of data addresses located in the external sequential ROM to the address space of the microprocessor contains the read data register, the address register and the state machine of the device for direct mapping of addresses.

EA201700120A 2014-09-30 2015-09-30 Device for direct mapping of data addresses located in the external serial rom into the address space of microprocessor core, computer system, and data transmission method EA038978B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU2014139279/08A RU2579949C2 (en) 2014-09-30 2014-09-30 Computer system
PCT/RU2015/000626 WO2016053146A1 (en) 2014-09-30 2015-09-30 Computer system

Publications (2)

Publication Number Publication Date
EA201700120A1 true EA201700120A1 (en) 2017-10-31
EA038978B1 EA038978B1 (en) 2021-11-17

Family

ID=53284988

Family Applications (1)

Application Number Title Priority Date Filing Date
EA201700120A EA038978B1 (en) 2014-09-30 2015-09-30 Device for direct mapping of data addresses located in the external serial rom into the address space of microprocessor core, computer system, and data transmission method

Country Status (3)

Country Link
EA (1) EA038978B1 (en)
RU (1) RU2579949C2 (en)
WO (1) WO2016053146A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016224747A1 (en) * 2016-12-12 2018-06-14 Robert Bosch Gmbh control unit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5535360A (en) * 1994-08-31 1996-07-09 Vlsi Technology, Inc. Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor
US6601167B1 (en) * 2000-01-14 2003-07-29 Advanced Micro Devices, Inc. Computer system initialization with boot program stored in sequential access memory, controlled by a boot loader to control and execute the boot program
JP2004334486A (en) * 2003-05-07 2004-11-25 Internatl Business Mach Corp <Ibm> Starting system using boot code and starting method
KR100693924B1 (en) * 2005-01-31 2007-03-12 삼성전자주식회사 Booting system using high speed serial interface and booting method of the same

Also Published As

Publication number Publication date
WO2016053146A1 (en) 2016-04-07
RU2579949C2 (en) 2016-04-10
RU2014139279A (en) 2015-05-27
EA038978B1 (en) 2021-11-17
WO2016053146A8 (en) 2016-07-28

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