DK144548B - SIGNAL SPEED VALUE DETECTOR ISSUED FOR ECONOPRESSION CONNECTION - Google Patents

Description

(19) DENMARK (W.

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^ (12) PUBLICATION WRITING (11) 1 (+4548 B

DIRECTORATE OF THE PATENT AND TRADEMARKET SYSTEM

(21) Application No. 1225/76 (51) | ntC | * R OA B 3/20 (22) Filing Date 19 Mar. 1976 6 01 R 19/30 (24) Race day 19 · ί0.8Χ “· 1976 (41) Aim. available 21. s ep. 1976 (44) Presented 22. tnar. 1982 (86) International Application No. "(86) International Filing Day" (85) Continuation Day - (62) Master Application No. "

(30) Priority Mar 20 1975 * 7508765, FR

(71) Applicant COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCA = TEL S.A., 75008 Paris, FR.

(72) Inventor Jean-Michel Durand, FR: Etienne _Penlcaud, FR.

(74) Representative International Patent Office, (54) Signal peak value detector, especially for echo suppressor decoupling.

The invention relates to a signal peak value detector comprising a memory, a first comparator for comparing the instantaneous value of the signal with a value stored in the memory, and a control circuit for changing the value stored in the memory. Such a detector can be used in all cases where one wishes to monitor a transmission HQ channel, whether the signal is analog or digital. A particular use case is the case where a four-wire telephone transmission is desired at any time to know the state of the one circuit for the purpose of k); J- to suppress the echoes or block the transmission of noise; when subscribed to. o. If the monitor is not in the process of speaking, which monitoring also usually involves a comparison of the signal levels in a subscriber's transmit and receive channel, g When you want to determine the level of a signal, you usually make an integration of the signal and a comparison of the integrated value with a given threshold which, moreover, allows to distinguish between the utility signal and the noise. While the processing of an analog signal under this principle does not cause any particular difficulties, it is found that the integration of a digital signal leads to complicated and costly circuits of the kind referred to in French patent application 71 39 022.

US Patent No. 3,896,273 discloses another solution to the task, which is better suited to form a digital echo suppression coupling. Instead of the integration, digital levels are detected and a comparison of these levels with a threshold. Each threshold is valid for 50 ms and all cells of the incoming signal amplitude are stored in these cells in these 50 ms intervals. At the end of this 50 ms interval, the threshold is replaced by the highest value found during this time period.

Such a coupling, although less expensive than an integrator, nevertheless requires a large capacity storage to be able to store a large number of separate values, as well as comparators with a large number of inputs.

Another coupling is known in which one also compares the instantaneous value of the incoming signal in digital form with a variable threshold value stored in a storage. When the moment value of the incoming signal is greater than. the threshold, or when the threshold has not changed for a given period of time, the instantaneous value forms the new threshold.

However, such a coupling, which is very simple, does not in itself allow the task to be satisfactorily solved, especially when used in an echo suppression circuit, and when attached to another coupling based on the successively stored threshold values and after a given function, provide values representing the envelope of the incoming signal. However, the combination of such two couplings is quite complicated and they form a slow-acting system, which may involve delays in the echo suppression.

The invention aims to overcome these disadvantages, and for this purpose, a signal peak value detector according to the invention is characterized by a damping circuit which gives a value equal to the stored value attenuated in a predetermined ratio and another comparator for comparing the moment value of the signal with a given threshold, a third comparator for comparing the moment value of the signal with the attenuated storage value, and a fourth comparator for comparing the attenuated storage value with the threshold value, and by controlling the circuit to change the value stored in the storage depending on the output signals of the comparators. such that - if the moment value is greater than or equal to the threshold given, the stored value is replaced by the instant value if it is greater than the stored value and the stored value if it has not changed in a given time period is replaced either by the instantaneous value, if this is s dry than or equal to the damped storage value, or otherwise replaced by c (a steamed storage value), and - in the case where the instantaneous value is less than the threshold value, if this condition has been present for a period less than another given time, and the storage contents have not changed in the first time period, the new value stored in the storage is either the attenuated storage value, if it is greater than or equal to the threshold value, or otherwise a fixed value not more than equal with the threshold value, while the new value stored in the storage, if the instantaneous value has been less than the threshold value lower than said other predetermined period, is constituted by a fixed value which is at most equal to the threshold value, forming the desired peak value stored in the storage.

The term "signal" as used herein has been used to indicate that the invention is not limited to a given physical representation form, as it applies to an analog signal whose amplitude, frequency or phase comprises the information whose peak value is to be detected, or for, and especially for, a digital representation of a variable variable, where the value is indicated by a set of bits that form a "word" and in binary code represents a sample value of an analog signal. In that case, the memory and the comparator will preferably be designed as digital circuits, while the given times are measured by a counter controlled from a clock signal encoder.

The invention is explained in more detail below with reference to the schematic drawing, in which fig. 1 is a block diagram of the detector of the invention; and FIG. 2 shows two diagrams for explaining the invention.

An input 1 receives an analog signal whose peak value is to be measured. This signal is supplied to an analog-digital converter 2 which, with regular rhythm, outputs in parallel the different bits in a word corresponding to a sample value of the incoming signal. The transducer is controlled either by means of a clock signal embedded in the transducer, or by means of an external clock signal. The clock signal, hereinafter referred to as H, is also used in a unit U which controls a memory 5 whose output 6 forms the output of the detector. The unit U comprises a switch 4 located in front of the bearing 5 and a control circuit 3 controlling the switch.

The switch 4 has four inputs A, B, C and D, one of which inputs is always connected to the bearing 5 through a contact arm.

The inputs A and B are connected to the output of the converter 2 and the output of the storage 5. respectively. The input C is connected to the output of the storage 5 4 through a damping link 7, which aims to give the output signal from the storage 5 a given damping. The input D is connected to a reference source 8 which defines the threshold.

The detector further comprises four comparators 9, 10, 11 and 12. The first three comparators 9, 10 and 11 compare the word from transducer 2 with the word from storage 5, respectively, the output value from the attenuator 7 and the threshold value from the source 8. The outputs F and G from the comparators 10 and 11 output to the control circuit 3 a binary signal equal to "1" when the value of the converter 2 is greater than or equal to the value to which it is compared, or otherwise a signal equal to "0". The output E of comparator 9 outputs to the control circuit a signal equal to "1" when the value of the converter 2 is greater than the stored value, or otherwise a signal equal to "0".

The comparator 12 compares the attenuated value of the attenuator 7 to the threshold value of the source 8, and its output L outputs to the control circuit 3 a binary signal equal to "0" or "1" depending on whether the attenuated value is less or greater. than the threshold.

The control circuit 3 comprises a logic circuit 15 as well as two counters 13 and 14, which count the clock pulses and are connected to the outputs E and G of the comparators 9 and 11 respectively.

The counter 13 has a count capacity corresponding to a given time period d. At the end of each count cycle, the counter returns to 0, at which time it starts counting again. Each time the signal at the output E is equal to "l", the counting cycle is interrupted and the counter 13 is reset. This counter outputs to logic circuit 15 a binary signal T equal to "1" to indicate that a complete counting cycle is completed.

The counter 14 has a counter capacity corresponding to another given time period d *. This counter is connected to the output G and is arranged so that when a level equal to "0" is maintained on this output, the clock pulses H count until it reaches its full capacity and then remain in this state.

If the signal above output G switches to "1", the counter returns to 0 and remains in this state as long as the signal above output G equals "1". The counter 14 outputs to the logic circuit 15 a binary signal T * equal to "0" to indicate that the counter has reached its full capacity.

The logic circuit 15 is connected to the outputs E, F, G and L of the comparators 9, 10, 11 and 12. respectively. is described in detail in that it is constructed with ordinary logic opening circuits. Its operation is shown in the following explanation.

The input Δ is connected to the contact arm of the switch 4 when G is at "1", E is at "1", or F and T are simultaneously at "1", ie. when one has the relation: G. (E + F. T) = 1

The input B is connected to the contact arm of the switch 4 when simultaneously having Τ 'on "1" and E and T on "0", i.e. when you have the relation: Τ '. E. T = 1

The input C is connected to the contact arm of the switch 4 when simultaneously having Τ ', T and L of "1" and F of "0", ie. when you have the relation: Τ '. T. L F = 1

The input D is connected to the contact arm of the switch 4 when Τ 'is set to "0" or T is set to "1" while G is simultaneously "0" and F is to "1" or when F and L are simultaneously at "0", i.e. when having the relation: Τ '+ T. (G. F + F. L) = 1

The operation of the detector described above is explained in greater detail below with reference to FIG. 2. The upper time diagram shows an example of an analog signal, while the lower time diagram shows the signal obtained at output 6 after a genome conversion to analog value. The analog signal may e.g. be the utility signal on a telephone line. The peak values attributable to the noise on the line are usually less than -31 dB, while the peak values corresponding to the utility signal exceed this threshold. The vaporizer links the value from the storage to a vaporizer of e.g. 6 dB. The given periods d and d ', that is, the periods during which the respective counters work, e.g. be at 50 ms.

It is assumed that the threshold value of -31 dB at time t is stored in memory 5. Counter 14 is then blocked in its maximum value and signal Τ 'is equal to "0". It will be seen that as soon as the signal according to the first time diagram of FIG. 2 exceeds this threshold, the switch 4 connects the input A to the memory and replaces the value originally stored in the memory with the arriving value. At each change of the value stored in the memory, the counter 13 is reset and the counter 14, which was reset at the first overrun, remains blocked at this value while the signal Τ 'is set to "1". Assuming that ten sample values of the signal on the upward edge are provided up to the peak value, the state of the storage changes ten times, with the storage eventually having the value corresponding to the peak at time t ^ · The next sample value which is less than the content of the storage causes a change in the level of the output E of the comparator 9, so the switch 4 switches to the input B. Since the signal shown is greater than the threshold, the counter 14 remains blocked at "0" and the signal Τ 'remains at " 1 ". The counter 13 is no longer reset and it continues to count.

In the illustrated embodiment, the entire counting cycle is reviewed up to time 6, without the arriving signal again reaching the peak value it had at time tg, or being less than the threshold. The counter 13 then gives a signal T of "1", whereby the switch arm switches to position A or to position C or to position D, depending on the levels of the respective outputs F, G and L from comparators 10, 11 and 12, and the counter 13 returns to its initial state. In the example shown, F is set to "0" and G and L are set to "1", which is why the switch establishes a connection with input C. It will be seen that the memory receives the value it contained earlier, dapsed by 6 dB.

A short time thereafter, ie. at time t ^, the incoming signal exceeds this vaporized value, at which time the stored value grows again until at time t,. again reaching a peak value. The period between t and t0 corresponds to a complete cycle of the counter 13, and in the memory the preceding peak value is replaced by the instantaneous value of the signal, which in the illustrated embodiment is greater than -31 dB and greater than the memory value at 6 dB.

In the time period between tg and tg, the incoming signal falls below the value -31 dB at time tg. Then counter 14 begins a counting cycle which is interrupted shortly after, and counter 14 is reset at time t ^ when the arriving signal again becomes greater than -31 dB. This short-term variation of the arriving signal below the threshold implies no change in the storage value.

From time tg, the memory value grows again in accordance with the oncoming signal up to a new peak value maintained between the times t ^ and t ^ for a given time d, corresponding to the counting cycle of counter 13. While this value is maintained, the arriving signal decreases at the time t ^ Q below the threshold, causing counter 14 to be re-enabled. The signal shown at this point has a rather long period of low amplitude noise, less than -31 dB, and the reduction of the storage value takes place in two temps: At time t ^ the value decreases by 6 dB and the new storage value is then greater than -31 dB. At time t ^ g, separated from time t ^ Q by time d ', the counter 14 reaches the end of its counting cycle, making the binary signal Τ' equal to "0", causing the threshold value to be recorded in the memory.

After this noise period, the arriving signal again exceeds the -31 dB threshold at time t ^ g, and counter 13 is reset along with counter 14. The memory value follows the increase of the arriving signal up to a new peak value at time t ^. Thereafter, the signal falls briefly below the threshold for time too short for counter 14 to complete a complete counting cycle. At time t ^ g, separated from time t ^ by time d, the contact arm of switch 4 switches to input C since the moment value of the arriving signal is less than the last, with 6 dB attenuated memory value which

Claims (2)

7 144548 is greater than the threshold. Then, in the example shown, the signal has a small amplitude, and after a new period d, where the attenuated memory value is maintained in the memory, the threshold value is recorded in the memory at time t ^. It should be noted that e.g. is not necessarily the threshold value to be recorded in the storage during the noise periods since any fixed value less than or equal to the threshold value can be recorded in the storage. X in case the arriving signal is already in digital form, the converter 2 is redundant. The described coupling can also be designed as a completely analog coupling, in that for the bearing 5 and the comparators, analog components can be selected. Such a detector can be used in telephone transmissions or in other technical areas where it is possible to detect the presence and level of a utility signal in the presence of noise. A signal peak value detector comprising a memory (5), a first comparator (9) for comparing the instantaneous value of the signal with a value stored in the memory, and a control circuit for changing the value stored in the memory, characterized in part by an attenuation circuit (7), which gives a value equal to the stored value attenuated in a predetermined ratio, first a second comparator (11) for comparing the moment value of the signal with a given threshold value, and a third comparator (10) for comparing the moment value of the signal with the attenuated storage value and fourth comparator (12) for comparing the attenuated storage value with the threshold value, and by controlling (U) to change the value stored in the storage depending on the output signals of the comparators in such a way that the stored value, if the instantaneous value is greater than or equal to the given threshold, is replaced by the instantaneous value if it is greater than the stored value and the stored v value, if it has not changed in a given period of time (d), is replaced either by the instantaneous value if it is greater than or equal to the dimmed stock value, or if it is replaced by the dimmed stock value, and - in that case, where the instantaneous value is less than the threshold value, if this condition has been present for a period less than another given period (d ') and the storage contents have not changed during the first period (d), the new value stored in the storage is either of the steamed storage value, if it is greater than or equal to the threshold value, or, otherwise, of a fixed value not exceeding the threshold value, while the new value stored in the storage if the instantaneous value has been less than the threshold value longer than said the second predetermined time period is constituted by a fixed value which is at most equal to the threshold value, the value stored in the storage forming the desired peak value.