GB1499635A - Peak level detector circuit - Google Patents

Abstract

1499635 Peak detector COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 22 March 1976 [20 March 1975] 11376/76 Heading G1U [Also in Division H4] In an arrangement for monitoring a signal level, particularly a speech level for control of an echo suppressor, a first comparator 9 compares the signal level, from 2, with the output of a memory 5 and a control unit 15 controls the entry of signals to the memory in accordance with the output of the first comparator 9, the output of a second comparator 10 which compares the input signal with the output of the memory after passage through attenuator 10, the output of a third comparator 11 which compares the signal input with the output of a low threshold device 8, the output of a fourth comparator which compares the attenuated memory output with the low threshold, and with the condition of two timing devices 13, 14, which are controlled by changes in the outputs of the first and third comparators respectively. In operation if the input level is above the low threshold, and above the value stored in the memory 5, the stored value is changed to the presently appearing input signal level; if the input signal level falls below the stored value and remains there - below for a first time period, provided by timing device 13, i.e. 50 m Sec the stored value is changed first to the larger of the attenuated stored value or the threshold value then, if the input signal falls below the threshold value and remains there for a time greater than a second time period i.e. 50 m Sec determined by the timing device 14, the stored value is changed to the threshold value, or a predetermined reference value below the stored value. As described the input signal is converted to digital binary form in a to d converter 2 and the memory and comparators all operate on the digital signals.