IE42518B1 - Peak level detector circuit - Google Patents

Abstract

1499635 Peak detector COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 22 March 1976 [20 March 1975] 11376/76 Heading G1U [Also in Division H4] In an arrangement for monitoring a signal level, particularly a speech level for control of an echo suppressor, a first comparator 9 compares the signal level, from 2, with the output of a memory 5 and a control unit 15 controls the entry of signals to the memory in accordance with the output of the first comparator 9, the output of a second comparator 10 which compares the input signal with the output of the memory after passage through attenuator 10, the output of a third comparator 11 which compares the signal input with the output of a low threshold device 8, the output of a fourth comparator which compares the attenuated memory output with the low threshold, and with the condition of two timing devices 13, 14, which are controlled by changes in the outputs of the first and third comparators respectively. In operation if the input level is above the low threshold, and above the value stored in the memory 5, the stored value is changed to the presently appearing input signal level; if the input signal level falls below the stored value and remains there - below for a first time period, provided by timing device 13, i.e. 50 m Sec the stored value is changed first to the larger of the attenuated stored value or the threshold value then, if the input signal falls below the threshold value and remains there for a time greater than a second time period i.e. 50 m Sec determined by the timing device 14, the stored value is changed to the threshold value, or a predetermined reference value below the stored value. As described the input signal is converted to digital binary form in a to d converter 2 and the memory and comparators all operate on the digital signals.

Description

The present invention relates to peak level detector circuits.

Such circuits are commonly used whenever there is a need to monitor or supervise the level of signal in a transmission channel. A typical example is the detection of speech in both channels of an echo suppressor at a four-wire/two-wire hybrid in a telephone network. Not only are the two levels of speech compared to each other, but they are also compared to a minimum threshold so that IO it is possible to block the transmission of noise as well as the transmission of echoes. Generally speaking such circuits have a rapid attack characteristic combined with a relatively slow decay characteristic, and both characteristics are determined by capacitor/resistor integrator networks.

When the signal is in digital form, integration becomes a complicated and expensive procedure as shown, for example in British Patent Specification No. 1,409,917 of 27th October, 1972.

The present invention provides a peak level detector circuit, which avoids the use of integration and preferred embodiments of which can be used as speech detectors in an echo suppressor in a telephone circuit. It is preferably realised using digital techniques. - 2 42518 The present invention provides a peak level detector circuit for providing an output signal representative of the peak level of an incident signal; the indicator circuit comprising: an input for said incident signal; a memory for storing said output signal; a digital attenuator connected to the memory to provide an attenuated signal whose value is equal to the output signal attenuated by a predetermined ratio; a source for a minimum threshold signal; a set of four comparators arranged to compare respectively the output signal with the incident signal and each of the three possible pairs of the trio of signals constituted by the incident signal, the attenuated signal and the minimum threshold signal; first and second timing means for counting respective first and second periods of time; and memory control means responsive, in operation, to the comparators and to the timing means to cause the memory to store the following values under the following conditions: first condition: when the incident signal has remained less than the minimum threshold for at least the first period of time the memory stores a minimum value signal as the output signal; where the minimum value signal is not greater than the minimum threshold signal; second condition: when the incident signal is greater than or equal to the minimum threshold signal and is greater than the output signal, the memory stores the incident signal as the new output signal, which thereby increases with the incident signal until the incident signal reaches a peak; third condition: when the incident signal is less than or equal to the stored peak, the memory continues to store the peak as the output signal for the duration of the second period of time, unless either of the first and the second conditions becomes applicable before the . second period of time is completed; and - fourth condition: when the third condition has existed for the duration of the second period of time, the memory control means determines which is the greatest of the said trio of signals and the memory stores as a new, reduced peak output signal the said greatest signal, or in the case of the minimum threshold signal being the greatest the said minimum value signal and the memory control means goes to whichever of the first three conditions is then applicable.

The incident signal may be the amplitude, phase or frequency of an analog signal coded especially for use with the peak level detector circuit, but the main application envisaged for the present invention is one in which digitally encoded amplitude samples are already made available for some other item of equipment, e.g. PCM telephone equipment.

The attack characteristic of the present detector circuit follows the rising portion of the incident signal exactly while the decay characteristic is a decay of the said predetermined amount once every second period of time, unless a sudden drop to the minimum threshold value is caused by the incident signal remaining below the minimum - 4 43S18 threshold for the duration of the first period of time.

An embodiment of the invention is described in more detail, by way of example with reference to the accompanying drawings in which:Figure 1 is a block diagram of a detector embodying the invention; and Figure 2 shows two curves for use in explaining the operation of the detector.

An input 1 receives an analog signal whose amplitude peaks are to be detected. The analog signal is applied to an analog-to-digital converter 2 which supplies a sequence of digitally encoded samples of the incident analog signal, in parallel form and at a rate H. Clock pulses at the rate H are also made directly available by the converter 2 and are used by a control unit U for timing purposes.

Parallel connections are represented in the figure by a set of oblique strokes crossing a single connecting line, but the number of bits is not related to the number of strokes.

The digitally encoded samples are applied to a first input position A of a four position switch 4 whose output is connected to a memory 5 and whose other input positions B, C and D are explained below. The output of the memory 5 constitutes the output 6 of the peak detector as a whole and is connected to the second input position B of the switch 4 and also to the input of a circuit 7 whose function is to attenuate the stored value by a predetermined fixed ratio e.g. by simple shifting, i.e. transposition of a binary encoded sample. The output of the circuit 7 is connected to the third input position C of the switch 4 whose fourth input position D is connected to the output of a minimum threshold source 8.

The switch 4 is controlled by a control assembly 3 to connect any one of the four multi-bit signal words at its inputs to the memory 5. For future reference the digitally encoded sample of the incident signal will be referred to as word W, the output signal stored in the memory 5 as word W', the attenuated signal as word (W'-fidB), and the minimum threshold signal as word W°.

The detector further comprises four comparators 9, 10, and 12. The first of these comparators, 9, compares the stored output signal with the incident signal and provides an output signal E of value ONE when the incident signal is greater than the stored output signal. The remaining three comparators 10, 11 and 12 are connected to receive the trio of signals constituted by the incident signal, the attenuated signal and the minimum threshold signal to perform respective comparisons on each of the three possible pairs of signals from the trio. The output F of the comparator 10 has the value ONE when the incident signal is greater than or equal to the attenuated output signal, the output G of the comparator 11 has the value ONE when the incident signal is greater than or equal to the minimum threshold signal, and the output L of the comparator 12 has the value ONE when the attenuated output signal is greater than or equal to the minimum threshold signal. In the contrary cases these outputs are ZERO.

These results are tabulated as follows:6 E=1 if W ~-W' F=1 if W >(W'-6dB) G=1 if w >w° L=1 if (W'-8dB)>w‘ The control assembly 3 comprises a logic unit 15 and two counters 14 and 13 arranged to count the clock pulses H. The first counter 14 has a counting capacity defining a first predetermined period of time d'. The first counter is connected to the output G so as to be enabled to count when G is at ZERO (i.e. when the incident signal is below the minimum threshold), and to be cleared to a count of zero when G is at ONE. The first counter stops counting when full and stays at maximum count until cleared. When it is at maximum count it delivers a logic signal Τ' which has the value ZERO, at other counts the signal Τ' has the value ONE.

The second counter 13 has a counting capacity defining a second predetermined period of time d, and at the end of each counting cycle it returns to a count of zero and continues to count beginning a new cycle. It supplies an output signal T which has a value ONE at the end of each count and a value ZERO otherwise. It is enabled to count by the output E being at ZERO and it is cleared to a count of zero when the output E is at ONE (i.e. when the incident signal is greater than stored output signal).

The logic unit 15 receives the signals E, F, G, L, T and Τ' and derives logic combinations therefrom to set the positions of the four position switch 4. The logic unit 15 - 7 4251 8 consists of simple combinations of AND gates, OR gates and inverters which are arranged to provide signals according to the following logic equations: A=G.(E+F.T) B=T'.T.E C=T'.T.L.F D=T‘+T.(G.+F.L) These can be interpreted in words as follows: A. The incident signal can only be selected if it is at least equal to the threshold (G=1) and evert then it will only be selected if it is greater than the stored output signal (E=l) or if at the end of a cycle of the second counter 13 (T=l), it is not less than the attenuated signal (F=l).

B. The output signal will be selected when the incident signal is not greater than the output signal (E=l) and neither of the counters is full (T'.T=1).

C. The attenuation signal will be selected at the end of the cycle of the second counter 13 (T=l) provided the first counter 14 is not full (T'=l) and the attenuated'signal is greater than the incident signal (F=l) and not less than the threshold (L=l).

D. The minimum threshold signal will be selected in any event after the incident signal has been less than the threshold for as long as the first predetermined period (T‘=l), and will also be selected at the end of a cycle of the second counter 13 (T=l) if the minimum threshold signal is greater than the greater - 8 4 2 518 of the incident signal and the attenuated signal (G.F+F.L=1).

These logic equations give rise to operation under four possible conditions: First condition: the incident signal has remained lower than the threshold (G=0) for longer than the first predetermined period of time d'. The first counter 14 is stopped at full count and delivers a signal T'=l. The input D is selected (minimum threshold). This condition is stable until the incident signal rises above the threshold.

Second condition: the incident signal rises above the threshold and keeps rising. For as long as the incident signal does not drop below the threshold the first counter 14 is held to zero count by the signal G=1 and for as long as the incident signal keeps ahead of the stored output signal the second counter 13 is held to zero count by the signal E=l. The input A is selected.

Third condition: the incident signal stops rising above the stored peak, this causes the signal E=1 and selects the position B to keep the memory at the peak value of the incident signal. The second counter 13 starts counting and generally the third condition is stable until the end of the counting cycle of the second counter 13 (in which case the fourth condition becomes applicable) or until the incident signal rises above the stored peak value (in which case the second condition becomes applicable). There is also the possibility that the first condition will become applicable, and this will generally happen only if the third condition has been arrived at from the fourth, see below.

Fourth condition:· the incident- signal has not been above the stored peak for a full count of the second counter 13. In this condition the greatest of the above-mentioned trio of signals is chosen to replace the old stored peak. If two or three of them are equal this detector circuit gives first preference to the incident signal and second preference to the attenuated signal; the minimum threshold signal is only chosen if it is indeed the largest of the trio.

The fourth condition only lasts for one clock period since the second counter 13 does not block on full count. The next condition.will either be the second condition with the incident signal selected as the new peak and currently rising, or the third with the new peak still being greater than the incident signal.

There is the possibility of a return to the first condition. Clearly if the incident signal has dropped below the minimum threshold and has remained there during the preceding period of the third condition there is a good chance that the first counter will reach its full count and send the system to the first condition. The exact timing depends on the relative durations of the first period of time d' and the second period of time d, and on the relative dispositions of the instants when each counter started to count.

The logic of the fourth condition applies at instants when T=l, and can be verified by checking against the logic equations for selecting positions A, C and D.

The four conditions described above do not explicitly account for the possibility that the incident signal will rise just to the threshold and no further during a first condition period. In that event the precise subsequent behaviour can be deduced from the logic equations given above, and depends on the position of the second counter 13 (which is cycling and might be at T-l i.e. fourth condition), but whatever happens the stored value does not drop below the minimum threshold and it spends some time in the third condition before returning to the first.

A concrete example of the behaviour of this peak detector circuit is now described with reference to Figure 2, in which the upper curve represents the level of the stored output signal. The minimum threshold is -31dB and the attenuated signal is attenuated by 6dB. The durations of the first and second periods of time are both equal to ms.

The circuit is initially in the first condition (incident signal has remained continuously below the minimum threshold of -31dB for longer than d' i.e. 50 ms and the output signal is therefore at the minimum threshold.

At time tl the incident signal rises above the minimum threshold and keeps rising, thereby giving rise to the second condition. The output signal follows the incident signal to its peak at t2.

Thereafter the incident signal drops below its peak of t2 but remains above the threshold. This leaves the circuit in the third condition with the previous peak as the output signal. At time t3 the second counter 13 has counted one full cycle of third condition and for one clock period the circuit is in fourth condition. In this example 43513 the attenuated old peak is greater than the incident signal and the output value steps down by 6dB to the attenuated value. The circuit returns to the third condition and begins counting a new 50 ms.

Shortly thereafter, at t4, the incident signal rises above the stored output signal and the circuit is therefore in the second condition again. The stored output signal therefore follows the incident signal to a new peak at time t5. Thereafter the incident signal drops below its t5 peak and the third condition is again operative. This time the incident signal is shown spending a short duration t6-t7 below the minimum threshold. This does not alter the third condition, and the only effect is to cause the first counter to count for a little while before being reset to zero at t7. At the end of the current third condition at time t8 (=t5+d) the incident signal is the largest of the trio of selectable signals and it is rising. The third condition, passing by way of the fourth condition at t8, is replaced by the second condition.

A new peak is reached at t9 and thereafter the circuit is in the third condition again, storing the value of the peak at t9. The incident signal rapidly drops below the minimum threshold at tlO, to stay there for quite a long time. The first counter starts counting, but the first effect on the circuit is at til when the second counter completes its cycle of duration d starting from t9. At this instant of fourth condition the attenuated signal is chosen and the circuit returns to the third condition with a reduced output signal. Shortly thereafter 43518 at tl2 the first counter reaches full count and is blocked there. This causes the circuit to return to the first condition with an output signal equal to the minimum threshold and the incident signal below the minimum threshold.

Sometime thereafter the incident signal again rises above the threshold, at tl3, and the output follows (in second condition) to the new peak at tl4. This new peak is stored for duration d until tl5 when it is replaced with the attenuated signal, i.e. peak less 6dB. The incident signal remains low and eventually stays below the threshold.

Thus a duration d later at tl6 the largest signal of the trio is the minimum threshold. This value is stored as the output signal and the system returns to the third condition for a while. However the first counter is counting and the system will soon take up the first condition, although this will cause no outwardly appreciable change to the behaviour of the circuit since it is already presenting the minimum signal as its output while in the third condition. Naturally, which ever condition (first or third) it happens to be in, it will follow a rising incident signal (second condition) as soon as one of sufficient amplitude arrives.

In the example described above it can be seen that the digital circuit described approximates to an analog peak detector circuit having a virtually instantaneous attack characteristic, a decay characteristic of 6dB per 50 ms, and an overriding switch to take it to its minimum value if the incident signal has been below the minimum threshold for too long. This approximation avoids the use of digital 43518 integrating circuits.

In a variant a distinction can be made between the minimum threshold signal as used for comparison with the incident signal and the attenuated signal, and a minimum value signal which is stored at an output signal. The minimum output value actually stored can be any fixed quantity which is not greater than the minimum threshold used for comparison. For example a further attenuator circuit could be inserted between the source 8 and the input D, while leaving the connections to the comparators unchanged. Another possibility for the minimum value signal is the smallest level which can be encoded in the encoding system used.

Claims (9)

1. CLAIMS:l. Λ peak level detector circuit for providing an output signal representative of the peak level of an incident signal; the indicator circuit comprising: an input for said incident signal; a memory for storing said output sicnal; a digital attenuator connected to the memory to provide an attenuated signal whose value is equal to the output signal attenuated by a nredetermined ratio; a source for a minimum threshold signal; a set of four comparators arranged to compare respectively the output signal with the incident signal and each of the three possible pairs of the trio of signals constituted by the incident signal, the attenuated signal and the minimum threshold signal; first and second timing means for counting respective first and second periods of time; and memory control means responsive, in operation, to the comparators and to the timing means to cause the memory to store the following values under the following conditions: -first condition: when the incident signal has remained less than the minimum threshold for at least the first period of time the memory stores a minimum value signal as the output signal; where the minimum value signal is not greater than the minimum threshold signal; -second condition: when the incident signal is greater than or equal to the minimum threshold signal and is greater than the output signal, the memory stores the incident sign.ij as the new output signal, which thereby increases with the incident signal until the incident 15 43518 signal reaches a peak; - third condition: when the incident signal is less than or equal to the stored peak, the memory continues to store the peak as the output signal for the duration of the second period of time, unless either of the first and the second conditions becomes applicable before the second period of time is completed; and fourth condition; when the third condition has existed for the duration of the second period of time, the memory control means determines which is the greatest of the said trio of signals and the memory stores as a new, reduced peak output signal the said greatest signal, or in the case of the minimum threshold signal being the greatest the said minimum value signal and the memory control means goes to whichever of the first three conditions is then applicable.

2. A peak level detector circuit according to claim 1 wherein the attenuator circuit performs its attenuation by shifting the digital signal applied to its input to perform division by a predetermined power of the number base of the encoding.

3. A peak level detector circuit according to claim 1 or 2 wherein the memory control means is arranged, when in the fourth condition and in the event of equality between any or all the pairs of the trio of signals, to select the incident signal in preference to either of the others and the attenuated signal in preference to the minimum threshold signal.

4. A peak level detector circuit according to any previous claim wherein the memory control means includes a four-position switch for selecting one of the four said signals as the input signal for the memory, a constant 5 value stored output signal being maintained by feeding the memory input from its output.

5. A peak level detector circuit according to any previous claim wherein the said minimum value signal, is equal to the minimum threshold signal; 10

6. A peak level detector circuit according to any previous claim wherein the said first and second periods of time are both of the order of 50 ms.

7. A peak level detector circuit according to any previous el^im wherein the minimum threshold value is of / 15 the order of -31dB.

8. A peak level detector circuit according to any previous claim wherein the predetermined attenuation ratio is 6dB.

9. A peak level detector circuit substantially as 20 herein described with reference to the accompanying drawings.