DK0598860T3 - - Google Patents

Info

Publication number
DK0598860T3
DK0598860T3 DK93907574.3T DK93907574T DK0598860T3 DK 0598860 T3 DK0598860 T3 DK 0598860T3 DK 93907574 T DK93907574 T DK 93907574T DK 0598860 T3 DK0598860 T3 DK 0598860T3
Authority
DK
Denmark
Prior art keywords
microprocessor
clock
substandard
slowed
wait
Prior art date
Application number
DK93907574.3T
Other languages
English (en)
Inventor
Robert H J Lee
John D Kenny
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Application granted granted Critical
Publication of DK0598860T3 publication Critical patent/DK0598860T3/da

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Logic Circuits (AREA)
  • General Induction Heating (AREA)
  • Power Sources (AREA)
  • Electronic Switches (AREA)
DK93907574.3T 1992-03-27 1993-03-25 DK0598860T3 (da)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/858,834 US5254888A (en) 1992-03-27 1992-03-27 Switchable clock circuit for microprocessors to thereby save power

Publications (1)

Publication Number Publication Date
DK0598860T3 true DK0598860T3 (da) 1997-03-17

Family

ID=25329312

Family Applications (1)

Application Number Title Priority Date Filing Date
DK93907574.3T DK0598860T3 (da) 1992-03-27 1993-03-25

Country Status (11)

Country Link
US (1) US5254888A (da)
EP (1) EP0598860B1 (da)
JP (1) JP2563888B2 (da)
AT (1) ATE143541T1 (da)
CA (1) CA2110048A1 (da)
DE (1) DE69305049T2 (da)
DK (1) DK0598860T3 (da)
ES (1) ES2095046T3 (da)
GR (1) GR3021719T3 (da)
TW (1) TW423670U (da)
WO (1) WO1993020618A1 (da)

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2570845B2 (ja) * 1988-05-27 1997-01-16 セイコーエプソン株式会社 情報処理装置
US5394527A (en) * 1991-05-17 1995-02-28 Zenith Data Systems Corporation Method and apparatus facilitating use of a hard disk drive in a computer system having suspend/resume capability
US5446904A (en) 1991-05-17 1995-08-29 Zenith Data Systems Corporation Suspend/resume capability for a protected mode microprocessor
US5652890A (en) * 1991-05-17 1997-07-29 Vantus Technologies, Inc. Interrupt for a protected mode microprocessor which facilitates transparent entry to and exit from suspend mode
US6193422B1 (en) * 1992-04-03 2001-02-27 Nec Corporation Implementation of idle mode in a suspend/resume microprocessor system
US5537660A (en) * 1992-04-17 1996-07-16 Intel Corporation Microcontroller having selectable bus timing modes based on primary and secondary clocks for controlling the exchange of data with memory
US5404459A (en) * 1992-07-21 1995-04-04 Advanced Micro Devices Serial interface module and method in which the clock is only activated to send a predetermined number of data bits
US5457414A (en) * 1992-12-22 1995-10-10 At&T Ipm Corp. Power supply loss sensor
US5357146A (en) * 1992-12-31 1994-10-18 At&T Bell Laboratories Glitch-free clock multiplexer
US5587675A (en) * 1993-08-12 1996-12-24 At&T Global Information Solutions Company Multiclock controller
US6052792A (en) * 1993-08-24 2000-04-18 Mensch, Jr.; William D. Power management and program execution location management system for CMOS microcomputer
US7216064B1 (en) 1993-09-21 2007-05-08 Intel Corporation Method and apparatus for programmable thermal sensor for an integrated circuit
US5483102A (en) * 1994-05-12 1996-01-09 Intel Corporation Employing on die temperature sensors and fan-heatsink failure signals to control power dissipation
US5752011A (en) 1994-06-20 1998-05-12 Thomas; C. Douglas Method and system for controlling a processor's clock frequency in accordance with the processor's temperature
US5615376A (en) * 1994-08-03 1997-03-25 Neomagic Corp. Clock management for power reduction in a video display sub-system
JP3475510B2 (ja) * 1994-08-09 2003-12-08 ヤマハ株式会社 省電力機能付き集積回路
US5583461A (en) * 1994-09-19 1996-12-10 Advanced Micro Devices, Inc. Internal clock signal generation circuit having external clock detection and a selectable internal clock pulse
US5771373A (en) * 1994-12-22 1998-06-23 Texas Instruments Incorporated Power management masked clock circuitry, systems and methods
US5729720A (en) * 1994-12-22 1998-03-17 Texas Instruments Incorporated Power management masked clock circuitry, systems and methods
US5754436A (en) * 1994-12-22 1998-05-19 Texas Instruments Incorporated Adaptive power management processes, circuits and systems
US5754837A (en) * 1994-12-22 1998-05-19 Texas Instruments Incorporated Clock control circuits, systems and methods
EP0727728A1 (en) * 1995-02-15 1996-08-21 International Business Machines Corporation Computer system power management
US5852737A (en) * 1995-04-24 1998-12-22 National Semiconductor Corporation Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down
US5659712A (en) * 1995-05-26 1997-08-19 National Semiconductor Corporation Pipelined microprocessor that prevents the cache from being read when the contents of the cache are invalid
US5815736A (en) * 1995-05-26 1998-09-29 National Semiconductor Corporation Area and time efficient extraction circuit
US5821910A (en) * 1995-05-26 1998-10-13 National Semiconductor Corporation Clock generation circuit for a display controller having a fine tuneable frame rate
US5546353A (en) * 1995-05-26 1996-08-13 National Semiconductor Corporation Partitioned decode circuit for low power operation
WO1996038773A2 (en) * 1995-05-26 1996-12-05 National Semiconductor Corporation Integrated primary bus and secondary bus controller with reduced pin count
US5752269A (en) * 1995-05-26 1998-05-12 National Semiconductor Corporation Pipelined microprocessor that pipelines memory requests to an external memory
US5541935A (en) * 1995-05-26 1996-07-30 National Semiconductor Corporation Integrated circuit with test signal buses and test control circuits
US5612637A (en) * 1995-05-26 1997-03-18 National Semiconductor Corporation Supply and interface configurable input/output buffer
US5682339A (en) * 1995-05-26 1997-10-28 National Semiconductor Corporation Method for performing rotate through carry using a 32 bit barrel shifter and counter
US5731812A (en) * 1995-05-26 1998-03-24 National Semiconductor Corp. Liquid crystal display (LCD) protection circuit
US5655139A (en) * 1995-05-26 1997-08-05 National Semiconductor Corporation Execution unit architecture to support X86 instruction set and X86 segmented addressing
EP1343076A3 (en) * 1995-05-26 2004-02-25 National Semiconductor Corporation integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitration
US5687102A (en) * 1995-05-26 1997-11-11 National Semiconductor Corp. Double precision (64 bit) shift operations using a 32 bit data path
US5617543A (en) * 1995-05-26 1997-04-01 National Semiconductor Corporation Non-arithmetical circular buffer cell availability status indicator circuit
DE69616718D1 (de) * 1995-05-26 2001-12-13 Nat Semiconductor Corp Vorrichtung und verfahren zur bestimmung von adressen fehlausgerichteter daten
US5583453A (en) * 1995-05-26 1996-12-10 National Semiconductor Corporation Incrementor/decrementor
US5598112A (en) * 1995-05-26 1997-01-28 National Semiconductor Corporation Circuit for generating a demand-based gated clock
US5699506A (en) * 1995-05-26 1997-12-16 National Semiconductor Corporation Method and apparatus for fault testing a pipelined processor
US5717909A (en) * 1995-05-26 1998-02-10 National Semiconductor Corporation Code breakpoint decoder
US5649147A (en) * 1995-05-26 1997-07-15 National Semiconductor Corporation Circuit for designating instruction pointers for use by a processor decoder
US5754460A (en) * 1995-05-26 1998-05-19 National Semiconductor Corporation Method for performing signed division
US5710939A (en) * 1995-05-26 1998-01-20 National Semiconductor Corporation Bidirectional parallel data port having multiple data transfer rates, master, and slave operation modes, and selective data transfer termination
US5680564A (en) * 1995-05-26 1997-10-21 National Semiconductor Corporation Pipelined processor with two tier prefetch buffer structure and method with bypass
US6237074B1 (en) 1995-05-26 2001-05-22 National Semiconductor Corp. Tagged prefetch and instruction decoder for variable length instruction set and method of operation
US5826106A (en) * 1995-05-26 1998-10-20 National Semiconductor Corporation High performance multifunction direct memory access (DMA) controller
US5696994A (en) * 1995-05-26 1997-12-09 National Semiconductor Corporation Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for operation in two different transfer modes
US5805923A (en) 1995-05-26 1998-09-08 Sony Corporation Configurable power management system having a clock stabilization filter that can be enabled or bypassed depending upon whether a crystal or can oscillator is used
US5652718A (en) * 1995-05-26 1997-07-29 National Semiconductor Corporation Barrel shifter
US5692146A (en) * 1995-05-26 1997-11-25 National Semiconductor Corporation Method of implementing fast 486TM microprocessor compatible string operations
US5831877A (en) * 1995-05-26 1998-11-03 National Semiconductor Corporation Bit searching through 8, 16, or 32 bit operands using a 32 bit data path
US5900886A (en) * 1995-05-26 1999-05-04 National Semiconductor Corporation Display controller capable of accessing an external memory for gray scale modulation data
US5901322A (en) * 1995-06-22 1999-05-04 National Semiconductor Corporation Method and apparatus for dynamic control of clocks in a multiple clock processor, particularly for a data cache
US5825648A (en) * 1996-03-26 1998-10-20 Casio Phonemate, Inc. Backup system for a time of day clock in an electronic device
JP3528413B2 (ja) * 1996-04-19 2004-05-17 ソニー株式会社 関数クロック発生回路並びにそれを用いたイネーブル機能付きｄ型フリップフロップおよび記憶回路
US5789952A (en) * 1996-05-01 1998-08-04 Cypress Semiconductor Corporation Anti-lock CPU clock control method, circuit and apparatus
JP3191720B2 (ja) * 1997-04-11 2001-07-23 日本電気株式会社 マルチプレクサ
US6928559B1 (en) * 1997-06-27 2005-08-09 Broadcom Corporation Battery powered device with dynamic power and performance management
US6271701B1 (en) * 1999-05-14 2001-08-07 Analog Devices, Inc. Resetting flip-flop structures and methods for high-rate trigger generation and event monitoring
US6166991A (en) 1999-11-03 2000-12-26 Cypress Semiconductor Corp. Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
JP3301422B2 (ja) * 1999-11-08 2002-07-15 日本電気株式会社 ディスプレイの駆動方法及びその回路
US7260731B1 (en) 2000-10-23 2007-08-21 Transmeta Corporation Saving power when in or transitioning to a static mode of a processor
US7085952B2 (en) * 2001-09-14 2006-08-01 Medtronic, Inc. Method and apparatus for writing data between fast and slow clock domains
US6988215B2 (en) * 2001-09-14 2006-01-17 Medtronic, Inc. Method and apparatus for synchronization of clock domains
US6865135B2 (en) * 2003-03-12 2005-03-08 Micron Technology, Inc. Multi-frequency synchronizing clock signal generator
US6975145B1 (en) * 2003-06-02 2005-12-13 Xilinx, Inc. Glitchless dynamic multiplexer with synchronous and asynchronous controls
US7129765B2 (en) 2004-04-30 2006-10-31 Xilinx, Inc. Differential clock tree in an integrated circuit
US7696290B2 (en) * 2004-12-03 2010-04-13 Crompton Corporation Aromatic sulfonic acids, amines, and nitrophenols in combination with nitroxyl radical-containing compounds or C-nitrosanilines as polymerization inhibitors
US8456193B2 (en) 2010-09-17 2013-06-04 Qualcomm Incorporated Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
US8909509B2 (en) * 2010-10-01 2014-12-09 Rockwell Automation Technologies, Inc. Dynamically selecting master clock to manage non-linear simulation clocks
US9225322B2 (en) 2013-12-17 2015-12-29 Micron Technology, Inc. Apparatuses and methods for providing clock signals

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5881334A (ja) * 1981-11-11 1983-05-16 Hitachi Ltd 情報処理装置
US4835681A (en) * 1984-06-27 1989-05-30 Compaq Computer Corporation Personal computer having normal and high speed execution modes
US4727491A (en) * 1984-06-27 1988-02-23 Compaq Computer Corporation Personal computer having normal and high speed execution modes
US4748417A (en) * 1985-02-05 1988-05-31 Siemens Aktiengesellschaft Method and circuit arrangement for switching a clock-controlled device having a plurality of operating statuses
GB8615399D0 (en) * 1986-06-24 1986-07-30 Int Computers Ltd Switching circuit
JP2643146B2 (ja) * 1987-05-14 1997-08-20 ソニー株式会社 マイクロコンピュータのクロック生成回路
JP2570845B2 (ja) * 1988-05-27 1997-01-16 セイコーエプソン株式会社 情報処理装置
US4965524A (en) * 1988-06-09 1990-10-23 National Semiconductor Corp. Glitch free clock select
GB2246455A (en) * 1990-07-23 1992-01-29 Philips Electronic Associated Altering the rate at which digital circuitry operates
US5155380A (en) * 1991-04-12 1992-10-13 Acer Incorporated Clock switching circuit and method for preventing glitch during switching

Also Published As

Publication number Publication date
US5254888A (en) 1993-10-19
DE69305049T2 (de) 1997-02-06
ATE143541T1 (de) 1996-10-15
CA2110048A1 (en) 1993-10-14
EP0598860A1 (en) 1994-06-01
WO1993020618A1 (en) 1993-10-14
EP0598860B1 (en) 1996-09-25
GR3021719T3 (en) 1997-02-28
EP0598860A4 (en) 1994-10-05
JP2563888B2 (ja) 1996-12-18
ES2095046T3 (es) 1997-02-01
TW423670U (en) 2001-02-21
DE69305049D1 (de) 1996-10-31
JPH06510648A (ja) 1994-11-24

Similar Documents

Publication Publication Date Title
DK0598860T3 (da)
GB9109445D0 (en) A circuit for glitch-free switching of asynchronous clock sources
DE3270984D1 (en) Low dissipation snubber circuit for switching power transistors
AU589789B2 (en) Integrated circuit clock bus system
EP0545392A3 (en) Synchronous circuit
EP0427527A3 (en) Offset correction circuit of pwm inverter
AU556946B2 (en) Inverter control circuit
EP0425951A3 (en) Ecl cutoff driver circuit with reduced standby power dissipation
DE69216036D1 (de) Bussteuerungsschaltung
JPS57158095A (en) Shift register circuit
KR920009495U (ko) 엘리베이터의 절전 제어회로
KR940027342U (ko) 모시계에 의한 자시계 제어회로
KR940004685U (ko) 전자레인지의 인버터 보호회로
KR920009805U (ko) 전자렌지의 인버터 출력제어회로
KR930015448U (ko) 무정전 전원장치의 인버터 제어회로
KR900001757U (ko) 인버터 제어회로
DE3377763D1 (en) Circuit arrangement for controlling the synchronous transmission of data
KR940004548U (ko) 동기용 시스템 클럭 전송회로
KR940003852U (ko) 인버터 회로를 이용한 전자렌지
ATA151990A (de) Ansteuerschaltung fuer pulsumrichter
KR940018619U (ko) 전자레인지의 인버터 회로
KR970006430Y1 (en) Protective circuit of inverter
KR940025199U (ko) 전자렌지의 출력제어회로
KR950012107U (ko) 전자레인지의 출력제어회로
KR900011183U (ko) 전자조리기의 인버어터용 파우어 트랜지스터 보호회로