DE926597T1 - Verfahren und Vorrichtung zur vollsichtbaren Ablaufverfolgung einer Emulation - Google Patents

Verfahren und Vorrichtung zur vollsichtbaren Ablaufverfolgung einer Emulation

Info

Publication number
DE926597T1
DE926597T1 DE0926597T DE97122560T DE926597T1 DE 926597 T1 DE926597 T1 DE 926597T1 DE 0926597 T DE0926597 T DE 0926597T DE 97122560 T DE97122560 T DE 97122560T DE 926597 T1 DE926597 T1 DE 926597T1
Authority
DE
Germany
Prior art keywords
enhanced
les
fpga
emulation
frozen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE0926597T
Other languages
English (en)
Other versions
DE19722560A1 (de
Inventor
Jean Barbier
Olivier Lepape
Frederic Reblewski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mentor Graphics Corp
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Publication of DE926597T1 publication Critical patent/DE926597T1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G01R31/318519—Test of field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
DE0926597T 1997-12-19 1997-12-19 Verfahren und Vorrichtung zur vollsichtbaren Ablaufverfolgung einer Emulation Pending DE926597T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97122560A EP0926597B1 (de) 1997-12-19 1997-12-19 Verfahren und Vorrichtung zur vollsichtbaren Ablaufverfolgung einer Emulation

Publications (1)

Publication Number Publication Date
DE926597T1 true DE926597T1 (de) 2000-03-09

Family

ID=8227843

Family Applications (2)

Application Number Title Priority Date Filing Date
DE0926597T Pending DE926597T1 (de) 1997-12-19 1997-12-19 Verfahren und Vorrichtung zur vollsichtbaren Ablaufverfolgung einer Emulation
DE69721787T Expired - Lifetime DE69721787T2 (de) 1997-12-19 1997-12-19 Verfahren und Vorrichtung zur vollsichtbaren Ablaufverfolgung einer Emulation

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69721787T Expired - Lifetime DE69721787T2 (de) 1997-12-19 1997-12-19 Verfahren und Vorrichtung zur vollsichtbaren Ablaufverfolgung einer Emulation

Country Status (2)

Country Link
EP (2) EP1306685A2 (de)
DE (2) DE926597T1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2873983B1 (de) * 2013-11-14 2016-11-02 Accemic GmbH & Co. KG Spurdatenverarbeitung und Profilierungsvorrichtung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0411904A3 (en) * 1989-07-31 1992-05-27 Texas Instruments Incorporated Processor condition sensing circuits, systems and methods
US5321828A (en) * 1991-06-07 1994-06-14 Step Engineering High speed microcomputer in-circuit emulator
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system

Also Published As

Publication number Publication date
EP0926597A1 (de) 1999-06-30
EP0926597B1 (de) 2003-05-07
DE69721787T2 (de) 2004-03-11
DE69721787D1 (de) 2003-06-12
EP1306685A2 (de) 2003-05-02

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