DE69939775D1 - Verfahren zur bildung zweifacher feldoxid-strukturen - Google Patents

Verfahren zur bildung zweifacher feldoxid-strukturen

Info

Publication number
DE69939775D1
DE69939775D1 DE69939775T DE69939775T DE69939775D1 DE 69939775 D1 DE69939775 D1 DE 69939775D1 DE 69939775 T DE69939775 T DE 69939775T DE 69939775 T DE69939775 T DE 69939775T DE 69939775 D1 DE69939775 D1 DE 69939775D1
Authority
DE
Germany
Prior art keywords
field oxide
forming double
oxide structures
double field
structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69939775T
Other languages
German (de)
English (en)
Inventor
Sun Yu
Tuan D Pham
Mark S Ramsbey
Chi Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69939775D1 publication Critical patent/DE69939775D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0128—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising multiple local oxidation process steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
DE69939775T 1998-03-06 1999-03-05 Verfahren zur bildung zweifacher feldoxid-strukturen Expired - Lifetime DE69939775D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/036,288 US5966618A (en) 1998-03-06 1998-03-06 Method of forming dual field isolation structures
PCT/US1999/004905 WO1999045589A1 (en) 1998-03-06 1999-03-05 Method of forming dual field isolation structures

Publications (1)

Publication Number Publication Date
DE69939775D1 true DE69939775D1 (de) 2008-12-04

Family

ID=21887749

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69939775T Expired - Lifetime DE69939775D1 (de) 1998-03-06 1999-03-05 Verfahren zur bildung zweifacher feldoxid-strukturen

Country Status (6)

Country Link
US (1) US5966618A (https=)
EP (1) EP1060510B1 (https=)
JP (1) JP2002506288A (https=)
KR (1) KR100537812B1 (https=)
DE (1) DE69939775D1 (https=)
WO (1) WO1999045589A1 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6249036B1 (en) * 1998-03-18 2001-06-19 Advanced Micro Devices, Inc. Stepper alignment mark formation with dual field oxide process
US6127247A (en) * 1998-06-03 2000-10-03 Texas Instruments - Acer Incorporated Method of eliminating photoresist outgassing in constructing CMOS vertically modulated wells by high energy ion implantation
US6362049B1 (en) * 1998-12-04 2002-03-26 Advanced Micro Devices, Inc. High yield performance semiconductor process flow for NAND flash memory products
US6383861B1 (en) 1999-02-18 2002-05-07 Micron Technology, Inc. Method of fabricating a dual gate dielectric
FR2810447B1 (fr) * 2000-06-16 2003-09-05 Commissariat Energie Atomique Procede de creation d'un etage de circuit integre ou conexistent des motifs fins et larges
US6750157B1 (en) 2000-10-12 2004-06-15 Advanced Micro Devices, Inc. Nonvolatile memory cell with a nitridated oxide layer
US6908817B2 (en) * 2002-10-09 2005-06-21 Sandisk Corporation Flash memory array with increased coupling between floating and control gates
US7183153B2 (en) * 2004-03-12 2007-02-27 Sandisk Corporation Method of manufacturing self aligned non-volatile memory cells
US7482223B2 (en) * 2004-12-22 2009-01-27 Sandisk Corporation Multi-thickness dielectric for semiconductor memory
US7202125B2 (en) * 2004-12-22 2007-04-10 Sandisk Corporation Low-voltage, multiple thin-gate oxide and low-resistance gate electrode
CN101090856B (zh) * 2004-12-29 2011-07-06 奥蒂斯电梯公司 在单一竖井内具有多个轿厢的电梯系统中的补偿
US7541240B2 (en) * 2005-10-18 2009-06-02 Sandisk Corporation Integration process flow for flash devices with low gap fill aspect ratio
EP3664151A1 (en) * 2018-12-06 2020-06-10 Nexperia B.V. Bipolar transistor with polysilicon emitter and method of manufacturing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3318213A1 (de) * 1983-05-19 1984-11-22 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum herstellen eines integrierten isolierschicht-feldeffekttransistors mit zur gateelektrode selbstausgerichteten kontakten
JPS62183164A (ja) * 1986-02-07 1987-08-11 Hitachi Ltd 半導体記憶装置およびその製造方法
US5061654A (en) * 1987-07-01 1991-10-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having oxide regions with different thickness
JPS6442164A (en) * 1987-08-07 1989-02-14 Fujitsu Ltd Semiconductor device and manufacture thereof
JP2512216B2 (ja) * 1989-08-01 1996-07-03 松下電器産業株式会社 半導体装置の製造方法
JPH04111465A (ja) * 1990-08-31 1992-04-13 Fujitsu Ltd 不揮発性半導体記憶装置の製造方法
FR2667440A1 (fr) * 1990-09-28 1992-04-03 Philips Nv Procede pour realiser des motifs d'alignement de masques.
US5110756A (en) * 1991-07-03 1992-05-05 At&T Bell Laboratories Method of semiconductor integrated circuit manufacturing which includes processing for reducing defect density
JPH08125006A (ja) * 1994-10-20 1996-05-17 Victor Co Of Japan Ltd 半導体装置及びその製造方法
JPH0997788A (ja) * 1995-07-21 1997-04-08 Rohm Co Ltd 半導体装置及びその製造方法
KR100214469B1 (ko) * 1995-12-29 1999-08-02 구본준 반도체소자의 격리막 형성방법
US5646063A (en) * 1996-03-28 1997-07-08 Advanced Micro Devices, Inc. Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device
US5794809A (en) * 1997-02-18 1998-08-18 Shuval; Shlomo Trash container with automatic liner bag feed

Also Published As

Publication number Publication date
WO1999045589A1 (en) 1999-09-10
EP1060510B1 (en) 2008-10-22
EP1060510A1 (en) 2000-12-20
KR20010041645A (ko) 2001-05-25
KR100537812B1 (ko) 2005-12-20
US5966618A (en) 1999-10-12
JP2002506288A (ja) 2002-02-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES, INC., GRAND CAYMANN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,