DE69933515D1 - Peripherieprozessor - Google Patents

Peripherieprozessor

Info

Publication number
DE69933515D1
DE69933515D1 DE69933515T DE69933515T DE69933515D1 DE 69933515 D1 DE69933515 D1 DE 69933515D1 DE 69933515 T DE69933515 T DE 69933515T DE 69933515 T DE69933515 T DE 69933515T DE 69933515 D1 DE69933515 D1 DE 69933515D1
Authority
DE
Germany
Prior art keywords
peripheral processor
processor
peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69933515T
Other languages
English (en)
Other versions
DE69933515T2 (de
Inventor
Robert Edmond Ober
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Publication of DE69933515D1 publication Critical patent/DE69933515D1/de
Application granted granted Critical
Publication of DE69933515T2 publication Critical patent/DE69933515T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
DE69933515T 1998-07-28 1999-05-31 Peripherieprozessor Expired - Lifetime DE69933515T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/124,183 US6202104B1 (en) 1998-07-28 1998-07-28 Processor having a clock driven CPU with static design
US124183 1998-07-28

Publications (2)

Publication Number Publication Date
DE69933515D1 true DE69933515D1 (de) 2006-11-23
DE69933515T2 DE69933515T2 (de) 2007-06-21

Family

ID=22413306

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69933515T Expired - Lifetime DE69933515T2 (de) 1998-07-28 1999-05-31 Peripherieprozessor

Country Status (3)

Country Link
US (1) US6202104B1 (de)
EP (1) EP0977125B1 (de)
DE (1) DE69933515T2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69908682T2 (de) * 1998-03-20 2004-05-13 Texas Instruments Inc., Dallas Prozessor mit Echtzeit-Ablaufsteuerung zur Fehlerbeseitigung ohne Fehlerbeseitigungsmonitor
JP3526009B2 (ja) * 1999-02-09 2004-05-10 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピュータ・システムにおける電力管理装置および電力管理方法
US7061904B2 (en) * 1999-09-13 2006-06-13 Infineon Technologies North America Corp. Integrated access device controller
US7100061B2 (en) 2000-01-18 2006-08-29 Transmeta Corporation Adaptive power control
US6968469B1 (en) 2000-06-16 2005-11-22 Transmeta Corporation System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
US7260731B1 (en) * 2000-10-23 2007-08-21 Transmeta Corporation Saving power when in or transitioning to a static mode of a processor
US7112978B1 (en) 2002-04-16 2006-09-26 Transmeta Corporation Frequency specific closed loop feedback control of integrated circuits
US7336090B1 (en) 2002-04-16 2008-02-26 Transmeta Corporation Frequency specific closed loop feedback control of integrated circuits
US7941675B2 (en) * 2002-12-31 2011-05-10 Burr James B Adaptive power control
US7642835B1 (en) * 2003-11-12 2010-01-05 Robert Fu System for substrate potential regulation during power-up in integrated circuits
US7949864B1 (en) 2002-12-31 2011-05-24 Vjekoslav Svilan Balanced adaptive body bias control
US7205758B1 (en) 2004-02-02 2007-04-17 Transmeta Corporation Systems and methods for adjusting threshold voltage
US7786756B1 (en) 2002-12-31 2010-08-31 Vjekoslav Svilan Method and system for latchup suppression
US7953990B2 (en) 2002-12-31 2011-05-31 Stewart Thomas E Adaptive power control based on post package characterization of integrated circuits
US7228242B2 (en) 2002-12-31 2007-06-05 Transmeta Corporation Adaptive power control based on pre package characterization of integrated circuits
US20050149771A1 (en) * 2003-11-07 2005-07-07 Seiko Epson Corporation Processor control circuit, information processing apparatus, and central processing unit
US7012461B1 (en) 2003-12-23 2006-03-14 Transmeta Corporation Stabilization component for a substrate potential regulation circuit
US7692477B1 (en) * 2003-12-23 2010-04-06 Tien-Min Chen Precise control component for a substrate potential regulation circuit
US7129771B1 (en) 2003-12-23 2006-10-31 Transmeta Corporation Servo loop for well bias voltage source
US7649402B1 (en) 2003-12-23 2010-01-19 Tien-Min Chen Feedback-controlled body-bias voltage source
US7859062B1 (en) 2004-02-02 2010-12-28 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7816742B1 (en) 2004-09-30 2010-10-19 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7562233B1 (en) 2004-06-22 2009-07-14 Transmeta Corporation Adaptive control of operating and body bias voltages
US7774625B1 (en) 2004-06-22 2010-08-10 Eric Chien-Li Sheng Adaptive voltage control by accessing information stored within and specific to a microprocessor
US7240137B2 (en) * 2004-08-26 2007-07-03 International Business Machines Corporation System and method for message delivery across a plurality of processors
JP2006172266A (ja) * 2004-12-17 2006-06-29 Matsushita Electric Ind Co Ltd ダイレクトメモリアクセスシステム
DE102006004346A1 (de) * 2006-01-30 2007-10-18 Deutsche Thomson-Brandt Gmbh Datenbusschnittstelle mit abschaltbarem Takt
US10067892B2 (en) 2015-03-06 2018-09-04 Microchip Technology Incorporated Microcontroller or microprocessor with dual mode interrupt
US10049830B2 (en) * 2015-06-26 2018-08-14 Amazon Technologies, Inc. Relay architecture for transferring from redundant power sources
EP3537293A1 (de) 2018-03-09 2019-09-11 Till I.D. GmbH Zeitlich deterministischer mikroprozessor und mikrocontroller
WO2022246636A1 (en) * 2021-05-25 2022-12-01 Yangtze Memory Technologies Co., Ltd. Method and apparatus for power saving in semiconductor devices

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0479887A4 (en) * 1989-06-30 1992-08-12 Poqet Computer Corporation Computer power management system
US5167024A (en) * 1989-09-08 1992-11-24 Apple Computer, Inc. Power management for a laptop computer with slow and sleep modes
IT1247641B (it) 1990-04-26 1994-12-28 St Microelectronics Srl Trasferimento di dati in modo dma durante fasi di risveglio durante lo stato di attesa per interruzione di un microprocessore con riduzione di consumo
JPH04130510A (ja) * 1990-09-21 1992-05-01 Hitachi Ltd 情報処理装置の省電力方式
US5894577A (en) * 1993-09-22 1999-04-13 Advanced Micro Devices, Inc. Interrupt controller with external in-service indication for power management within a computer system
US5706407A (en) * 1993-12-28 1998-01-06 Kabushiki Kaisha Toshiba System for reallocation of memory banks in memory sized order
US5442775A (en) * 1994-02-08 1995-08-15 Meridian Semiconductor, Inc. Two clock microprocessor design with stall
US5493684A (en) 1994-04-06 1996-02-20 Advanced Micro Devices Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility
KR960012838B1 (ko) * 1994-06-20 1996-09-24 삼성전자 주식회사 스톱 클럭 제어장치와 그 방법
US5592173A (en) * 1994-07-18 1997-01-07 Trimble Navigation, Ltd GPS receiver having a low power standby mode
JPH08211960A (ja) 1995-01-31 1996-08-20 Mitsubishi Electric Corp マイクロコンピュータ
US5553236A (en) * 1995-03-03 1996-09-03 Motorola, Inc. Method and apparatus for testing a clock stopping/starting function of a low power mode in a data processor
US5774701A (en) * 1995-07-10 1998-06-30 Hitachi, Ltd. Microprocessor operating at high and low clok frequencies
US5737516A (en) * 1995-08-30 1998-04-07 Motorola, Inc. Data processing system for performing a debug function and method therefor
JP3621497B2 (ja) * 1996-03-01 2005-02-16 株式会社東芝 コンピュータシステム及び同システムにおけるクロック停止信号制御方法
US5848281A (en) * 1996-07-23 1998-12-08 Smalley; Kenneth George Method and apparatus for powder management in a multifunction controller with an embedded microprocessor

Also Published As

Publication number Publication date
EP0977125A1 (de) 2000-02-02
EP0977125B1 (de) 2006-10-11
US6202104B1 (en) 2001-03-13
DE69933515T2 (de) 2007-06-21

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