DE69907800D1 - Schnelle DRAM-Anordnung - Google Patents

Schnelle DRAM-Anordnung

Info

Publication number
DE69907800D1
DE69907800D1 DE69907800T DE69907800T DE69907800D1 DE 69907800 D1 DE69907800 D1 DE 69907800D1 DE 69907800 T DE69907800 T DE 69907800T DE 69907800 T DE69907800 T DE 69907800T DE 69907800 D1 DE69907800 D1 DE 69907800D1
Authority
DE
Germany
Prior art keywords
fast dram
dram arrangement
arrangement
fast
dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69907800T
Other languages
English (en)
Other versions
DE69907800T2 (de
Inventor
Michel Harrand
Richard Ferrant
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE69907800D1 publication Critical patent/DE69907800D1/de
Publication of DE69907800T2 publication Critical patent/DE69907800T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
DE69907800T 1998-03-26 1999-03-26 Schnelle DRAM-Anordnung Expired - Fee Related DE69907800T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9804008A FR2776819B1 (fr) 1998-03-26 1998-03-26 Dram a structure rapide
FR9804008 1998-03-26

Publications (2)

Publication Number Publication Date
DE69907800D1 true DE69907800D1 (de) 2003-06-18
DE69907800T2 DE69907800T2 (de) 2004-04-08

Family

ID=9524716

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69907800T Expired - Fee Related DE69907800T2 (de) 1998-03-26 1999-03-26 Schnelle DRAM-Anordnung

Country Status (4)

Country Link
US (1) US6215706B1 (de)
EP (1) EP0952587B1 (de)
DE (1) DE69907800T2 (de)
FR (1) FR2776819B1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2817997B1 (fr) * 2000-12-08 2003-03-21 St Microelectronics Sa Test d'une dram a lecture par cache
FR2817996B1 (fr) * 2000-12-08 2003-09-26 St Microelectronics Sa Memoire cache a cellules dram
US6567329B2 (en) 2001-08-28 2003-05-20 Intel Corporation Multiple word-line accessing and accessor
JP2003233986A (ja) * 2002-02-07 2003-08-22 Sony Corp 半導体記憶装置
US6738301B2 (en) 2002-08-29 2004-05-18 Micron Technology, Inc. Method and system for accelerating coupling of digital signals
US7342835B2 (en) * 2005-04-14 2008-03-11 Winbond Electronics Corp. Memory device with pre-fetch circuit and pre-fetch method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57117168A (en) * 1981-01-08 1982-07-21 Nec Corp Memory circuit
US4649516A (en) * 1984-06-01 1987-03-10 International Business Machines Corp. Dynamic row buffer circuit for DRAM
US5226147A (en) * 1987-11-06 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device for simple cache system
JP2564046B2 (ja) * 1991-02-13 1996-12-18 株式会社東芝 半導体記憶装置
KR0123850B1 (ko) * 1994-04-15 1997-11-25 문정환 디지탈 영상 메모리

Also Published As

Publication number Publication date
FR2776819B1 (fr) 2001-11-02
EP0952587B1 (de) 2003-05-14
DE69907800T2 (de) 2004-04-08
EP0952587A1 (de) 1999-10-27
FR2776819A1 (fr) 1999-10-01
US6215706B1 (en) 2001-04-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee