DE69841429D1 - Feinstruktur und Verfahren zu ihrer Herstellung - Google Patents

Feinstruktur und Verfahren zu ihrer Herstellung

Info

Publication number
DE69841429D1
DE69841429D1 DE69841429T DE69841429T DE69841429D1 DE 69841429 D1 DE69841429 D1 DE 69841429D1 DE 69841429 T DE69841429 T DE 69841429T DE 69841429 T DE69841429 T DE 69841429T DE 69841429 D1 DE69841429 D1 DE 69841429D1
Authority
DE
Germany
Prior art keywords
preparation
fine structure
fine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69841429T
Other languages
English (en)
Inventor
Yutaka Wakayama
Shun-Ichiro Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Japan Science and Technology Agency
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Science and Technology Agency filed Critical Japan Science and Technology Agency
Application granted granted Critical
Publication of DE69841429D1 publication Critical patent/DE69841429D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02425—Conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02645—Seed materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02653—Vapour-liquid-solid growth

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
DE69841429T 1997-06-11 1998-06-10 Feinstruktur und Verfahren zu ihrer Herstellung Expired - Lifetime DE69841429D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15365197A JP3452764B2 (ja) 1997-06-11 1997-06-11 超微細突起構造体の製造方法

Publications (1)

Publication Number Publication Date
DE69841429D1 true DE69841429D1 (de) 2010-02-25

Family

ID=15567208

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69841429T Expired - Lifetime DE69841429D1 (de) 1997-06-11 1998-06-10 Feinstruktur und Verfahren zu ihrer Herstellung

Country Status (4)

Country Link
US (1) US6025604A (de)
EP (1) EP0884768B1 (de)
JP (1) JP3452764B2 (de)
DE (1) DE69841429D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6653653B2 (en) 2001-07-13 2003-11-25 Quantum Logic Devices, Inc. Single-electron transistors and fabrication methods in which a projecting feature defines spacing between electrodes
US6483125B1 (en) * 2001-07-13 2002-11-19 North Carolina State University Single electron transistors in which the thickness of an insulating layer defines spacing between electrodes
JP4673070B2 (ja) * 2005-01-20 2011-04-20 日本電信電話株式会社 微小構造の成長制御方法
KR100849418B1 (ko) 2007-05-10 2008-08-01 한양대학교 산학협력단 코발트 피티 나노입자 형성방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5006914A (en) * 1988-12-02 1991-04-09 Advanced Technology Materials, Inc. Single crystal semiconductor substrate articles and semiconductor devices comprising same
JP2821061B2 (ja) * 1992-05-22 1998-11-05 電気化学工業株式会社 単結晶の製造方法
WO1995028741A1 (de) * 1994-04-19 1995-10-26 Siemens Aktiengesellschaft Mikroelektronisches bauelement und verfahren zu dessen herstellung
JPH09132500A (ja) * 1995-11-10 1997-05-20 Sony Corp 三角錐形状半導体構造とこれを用いた光学素子
US5976957A (en) * 1996-10-28 1999-11-02 Sony Corporation Method of making silicon quantum wires on a substrate

Also Published As

Publication number Publication date
EP0884768B1 (de) 2010-01-06
JPH113988A (ja) 1999-01-06
EP0884768A2 (de) 1998-12-16
EP0884768A3 (de) 2000-01-05
JP3452764B2 (ja) 2003-09-29
US6025604A (en) 2000-02-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition