DE69841104D1 - Herstellungsverfahren für eine SOI-Scheibe - Google Patents
Herstellungsverfahren für eine SOI-ScheibeInfo
- Publication number
- DE69841104D1 DE69841104D1 DE69841104T DE69841104T DE69841104D1 DE 69841104 D1 DE69841104 D1 DE 69841104D1 DE 69841104 T DE69841104 T DE 69841104T DE 69841104 T DE69841104 T DE 69841104T DE 69841104 D1 DE69841104 D1 DE 69841104D1
- Authority
- DE
- Germany
- Prior art keywords
- production process
- soi disk
- soi
- disk
- production
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98830743A EP1009024B1 (de) | 1998-12-10 | 1998-12-10 | Herstellungsverfahren für eine SOI-Scheibe |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69841104D1 true DE69841104D1 (de) | 2009-10-08 |
Family
ID=8236913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69841104T Expired - Lifetime DE69841104D1 (de) | 1998-12-10 | 1998-12-10 | Herstellungsverfahren für eine SOI-Scheibe |
Country Status (4)
Country | Link |
---|---|
US (1) | US6506663B1 (de) |
EP (1) | EP1009024B1 (de) |
JP (1) | JP2000183317A (de) |
DE (1) | DE69841104D1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10143936A1 (de) * | 2001-09-07 | 2003-01-09 | Infineon Technologies Ag | Verfahren zur Bildung eines SOI-Substrats, vertikaler Transistor und Speicherzelle mit vertikalem Transistor |
EP1294018A1 (de) * | 2001-09-17 | 2003-03-19 | Infineon Technologies AG | Silizium-auf-Isolator-Substrat und Herstellungsverfahren |
US20050100601A1 (en) * | 2003-11-07 | 2005-05-12 | Viratox, L.L.C. | Virucidal activities of cetylpyridinium chloride |
US7101806B2 (en) * | 2004-10-15 | 2006-09-05 | International Business Machines Corporation | Deep trench formation in semiconductor device fabrication |
US8344453B2 (en) * | 2007-10-18 | 2013-01-01 | Nxp B.V. | Method of manufacturing localized semiconductor-on-insulator (SOI) structures in a bulk semiconductor wafer |
CN106241731A (zh) * | 2016-08-25 | 2016-12-21 | 华东光电集成器件研究所 | 一种平板电容mems器件电容间隙的控制制备方法 |
SG11201913769RA (en) * | 2017-07-14 | 2020-01-30 | Sunedison Semiconductor Ltd | Method of manufacture of a semiconductor on insulator structure |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2156149A (en) * | 1984-03-14 | 1985-10-02 | Philips Electronic Associated | Dielectrically-isolated integrated circuit manufacture |
US5688655A (en) * | 1988-02-10 | 1997-11-18 | Ict Pharmaceuticals, Inc. | Method of screening for protein inhibitors and activators |
JP2879623B2 (ja) * | 1991-07-26 | 1999-04-05 | 富士写真フイルム株式会社 | カラー感光材料 |
JP3153632B2 (ja) * | 1992-06-11 | 2001-04-09 | ローム株式会社 | Soi構造の製造方法 |
US5472904A (en) * | 1994-03-02 | 1995-12-05 | Micron Technology, Inc. | Thermal trench isolation |
US5719085A (en) * | 1995-09-29 | 1998-02-17 | Intel Corporation | Shallow trench isolation technique |
US6114741A (en) * | 1996-12-13 | 2000-09-05 | Texas Instruments Incorporated | Trench isolation of a CMOS structure |
US5763315A (en) * | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
US6103635A (en) * | 1997-10-28 | 2000-08-15 | Fairchild Semiconductor Corp. | Trench forming process and integrated circuit device including a trench |
US6093611A (en) * | 1997-12-19 | 2000-07-25 | Advanced Micro Devices, Inc. | Oxide liner for high reliability with reduced encroachment of the source/drain region |
EP0948034B1 (de) * | 1998-04-03 | 2005-01-05 | STMicroelectronics S.r.l. | Ein Verfahren für die Herstellung einer SO1-Scheibe |
US6100163A (en) * | 1999-01-07 | 2000-08-08 | Taiwan Semiconductor Manufacturing Company | Gap filling of shallow trench isolation by ozone-tetraethoxysilane |
-
1998
- 1998-12-10 DE DE69841104T patent/DE69841104D1/de not_active Expired - Lifetime
- 1998-12-10 EP EP98830743A patent/EP1009024B1/de not_active Expired - Lifetime
-
1999
- 1999-12-08 US US09/457,623 patent/US6506663B1/en not_active Expired - Lifetime
- 1999-12-10 JP JP11350981A patent/JP2000183317A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP1009024A1 (de) | 2000-06-14 |
EP1009024B1 (de) | 2009-08-26 |
US6506663B1 (en) | 2003-01-14 |
JP2000183317A (ja) | 2000-06-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE60038856D1 (de) | Herstellungsverfahren für Toner | |
DE69925767D1 (de) | Tonerherstellungsverfahren | |
DE69936601D1 (de) | Tonerherstellungsverfahren | |
DE69926924D1 (de) | Tonerherstellungsverfahren | |
DE69527250D1 (de) | Herstellungsverfahren für bioabbaubare Blockcopolyester | |
DE59811004D1 (de) | Herstellungsverfahren für mikromechanische vorrichtung | |
DE69822424D1 (de) | Produktionsverfahren für Polycarbonat | |
ATE239683T1 (de) | Herstellungsverfahren für para-xylen | |
DE69916904D1 (de) | Tonerherstellungsverfahren | |
DE60040128D1 (de) | Optischer mikro-ausleger, herstellungsverfahren für einen solchen und mikro-ausleger-halter | |
DE69737340D1 (de) | Herstellungsverfahren für eine LED | |
BR9703977A (pt) | Processo para produção de polisoolefinas altamente ramificadas | |
DE69839906D1 (de) | Herstellungsverfahren für eine integrierte Schaltung | |
DE69919810D1 (de) | Tonerherstellungsverfahren | |
DE69927893T2 (de) | Tonerherstellungsverfahren | |
DE69826865D1 (de) | Herstellungsverfahren für verkapselte halbleiteranordnungen | |
DE69841104D1 (de) | Herstellungsverfahren für eine SOI-Scheibe | |
AR028078A1 (es) | Proceso para la produccion de grrnulos de enzimas | |
DE69709481D1 (de) | Herstellungsverfahren für Schokolade | |
ATE249436T1 (de) | Herstellungsverfahren | |
DE69623788D1 (de) | Herstellungsverfahren für einen Gegenstand | |
DE69942258D1 (de) | Tonerherstellungsverfahren | |
DE69808513D1 (de) | Herstellungsverfahren für meta-xylol | |
PT1049723E (pt) | Processo para o fabrico de inulina de chicoria | |
DE59910398D1 (de) | Herstellverfahren für mikromechanische bauelemente |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |