DE69839579D1 - Verbesserte Techniken für Ätzung einer Schicht auf Basis von Siliziumdioxid - Google Patents

Verbesserte Techniken für Ätzung einer Schicht auf Basis von Siliziumdioxid

Info

Publication number
DE69839579D1
DE69839579D1 DE69839579T DE69839579T DE69839579D1 DE 69839579 D1 DE69839579 D1 DE 69839579D1 DE 69839579 T DE69839579 T DE 69839579T DE 69839579 T DE69839579 T DE 69839579T DE 69839579 D1 DE69839579 D1 DE 69839579D1
Authority
DE
Germany
Prior art keywords
etching
silica
layer based
improved techniques
techniques
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69839579T
Other languages
English (en)
Inventor
Markus M Kirchhoff
Jochen Hanebeck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE69839579D1 publication Critical patent/DE69839579D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • ing And Chemical Polishing (AREA)
DE69839579T 1997-09-29 1998-08-20 Verbesserte Techniken für Ätzung einer Schicht auf Basis von Siliziumdioxid Expired - Lifetime DE69839579D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/939,216 US5866485A (en) 1997-09-29 1997-09-29 Techniques for etching a silicon dioxide-containing layer

Publications (1)

Publication Number Publication Date
DE69839579D1 true DE69839579D1 (de) 2008-07-17

Family

ID=25472762

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69839579T Expired - Lifetime DE69839579D1 (de) 1997-09-29 1998-08-20 Verbesserte Techniken für Ätzung einer Schicht auf Basis von Siliziumdioxid

Country Status (7)

Country Link
US (1) US5866485A (de)
EP (1) EP0905757B1 (de)
JP (1) JPH11162951A (de)
KR (1) KR100616178B1 (de)
CN (1) CN1130760C (de)
DE (1) DE69839579D1 (de)
TW (1) TW405185B (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5928967A (en) * 1996-06-10 1999-07-27 International Business Machines Corporation Selective oxide-to-nitride etch process using C4 F8 /CO/Ar
US6010968A (en) * 1998-12-24 2000-01-04 United Microelectronics Corp. Method for forming a contact opening with multilevel etching
US7541270B2 (en) * 2002-08-13 2009-06-02 Micron Technology, Inc. Methods for forming openings in doped silicon dioxide
US8673770B2 (en) * 2011-10-25 2014-03-18 Globalfoundries Inc. Methods of forming conductive structures in dielectric layers on an integrated circuit device
US10304692B1 (en) 2017-11-28 2019-05-28 International Business Machines Corporation Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits
CN110890277B (zh) * 2018-09-07 2022-05-10 无锡华润上华科技有限公司 沟槽式金属氧化物半导体肖特基势垒晶体管制备方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4376672A (en) * 1981-10-26 1983-03-15 Applied Materials, Inc. Materials and methods for plasma etching of oxides and nitrides of silicon
JPS58150429A (ja) * 1982-03-03 1983-09-07 Hitachi Ltd ドライエツチング方法
KR910010516A (ko) * 1989-11-15 1991-06-29 아오이 죠이치 반도체 메모리장치
JP3038950B2 (ja) * 1991-02-12 2000-05-08 ソニー株式会社 ドライエッチング方法
JPH0541365A (ja) * 1991-08-02 1993-02-19 Mitsubishi Electric Corp 半導体装置の製造方法
US5445712A (en) * 1992-03-25 1995-08-29 Sony Corporation Dry etching method
JP2720763B2 (ja) * 1993-09-17 1998-03-04 日本電気株式会社 半導体装置の製造方法
JPH07161702A (ja) * 1993-10-29 1995-06-23 Applied Materials Inc 酸化物のプラズマエッチング方法
JP3778299B2 (ja) * 1995-02-07 2006-05-24 東京エレクトロン株式会社 プラズマエッチング方法
JPH0982688A (ja) * 1995-09-19 1997-03-28 Sony Corp ドライエッチング方法
JPH09129612A (ja) * 1995-10-26 1997-05-16 Tokyo Electron Ltd エッチングガス及びエッチング方法
US5700737A (en) * 1996-02-26 1997-12-23 Taiwan Semiconductor Manufactured Company Ltd. PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination
TW335517B (en) * 1996-03-01 1998-07-01 Hitachi Ltd Apparatus and method for processing plasma
US5843847A (en) * 1996-04-29 1998-12-01 Applied Materials, Inc. Method for etching dielectric layers with high selectivity and low microloading
JPH1116886A (ja) * 1997-06-23 1999-01-22 Hitachi Ltd エッチング方法

Also Published As

Publication number Publication date
EP0905757A3 (de) 2000-10-25
CN1213161A (zh) 1999-04-07
JPH11162951A (ja) 1999-06-18
KR100616178B1 (ko) 2006-10-24
EP0905757B1 (de) 2008-06-04
CN1130760C (zh) 2003-12-10
US5866485A (en) 1999-02-02
KR19990030132A (ko) 1999-04-26
EP0905757A2 (de) 1999-03-31
TW405185B (en) 2000-09-11

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8364 No opposition during term of opposition