DE69839194D1 - Gerät und verfahren zum initieren hardwarevorrangsmanagement durch softwarekontrollierten registerzugriff - Google Patents

Gerät und verfahren zum initieren hardwarevorrangsmanagement durch softwarekontrollierten registerzugriff

Info

Publication number
DE69839194D1
DE69839194D1 DE69839194T DE69839194T DE69839194D1 DE 69839194 D1 DE69839194 D1 DE 69839194D1 DE 69839194 T DE69839194 T DE 69839194T DE 69839194 T DE69839194 T DE 69839194T DE 69839194 D1 DE69839194 D1 DE 69839194D1
Authority
DE
Germany
Prior art keywords
software
register access
force management
controlled register
initiating hardware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69839194T
Other languages
English (en)
Other versions
DE69839194T2 (de
Inventor
Muthurajan Jayakumar
Vijay Kumar Goru
Ravi Eakambaram
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69839194D1 publication Critical patent/DE69839194D1/de
Publication of DE69839194T2 publication Critical patent/DE69839194T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE69839194T 1997-12-31 1998-12-22 Gerät und verfahren zum initieren hardwarevorrangsmanagement durch softwarekontrollierten registerzugriff Expired - Lifetime DE69839194T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/001,817 US6298410B1 (en) 1997-12-31 1997-12-31 Apparatus and method for initiating hardware priority management by software controlled register access
PCT/US1998/027514 WO1999034298A1 (en) 1997-12-31 1998-12-22 Apparatus and method for initiating hardware priority management by software controlled register access
US1817 2007-11-05

Publications (2)

Publication Number Publication Date
DE69839194D1 true DE69839194D1 (de) 2008-04-10
DE69839194T2 DE69839194T2 (de) 2009-03-26

Family

ID=21697969

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69839194T Expired - Lifetime DE69839194T2 (de) 1997-12-31 1998-12-22 Gerät und verfahren zum initieren hardwarevorrangsmanagement durch softwarekontrollierten registerzugriff

Country Status (6)

Country Link
US (1) US6298410B1 (de)
EP (1) EP1049985B1 (de)
CN (1) CN1328677C (de)
AU (1) AU2012599A (de)
DE (1) DE69839194T2 (de)
WO (1) WO1999034298A1 (de)

Families Citing this family (28)

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Publication number Priority date Publication date Assignee Title
US6202090B1 (en) * 1997-12-11 2001-03-13 Cisco Technology, Inc. Apparatus and method for downloading core file in a network device
JP2000010800A (ja) * 1998-06-19 2000-01-14 Toshiba Corp 計算機システムに於けるスレッド制御装置、及び同システムに於けるスレッド制御方法
US6553443B1 (en) * 1999-09-28 2003-04-22 Legerity, Inc. Method and apparatus for prioritizing interrupts in a communication system
KR100317237B1 (ko) * 1999-10-01 2001-12-22 윤종용 유사 벡터 방식의 인터럽트 컨트롤러 및 그것의 인터럽트 처리 방법
US6754754B1 (en) * 1999-12-30 2004-06-22 Intel Corporation Apparatus and method for end of interrupt handling
JP2002055830A (ja) * 2000-05-29 2002-02-20 Seiko Epson Corp 割込信号生成装置及び割込信号の生成方法
JP4600586B2 (ja) * 2000-05-29 2010-12-15 セイコーエプソン株式会社 割込信号生成装置及び割込信号の生成方法
US6647441B1 (en) * 2000-09-15 2003-11-11 Hewlett-Packard Development Company, L.P. Method of maximizing servicing capability of large numbers of I/O descriptors
DE10062996B4 (de) * 2000-12-16 2005-09-29 Micronas Gmbh Unterbrecher-Steuereinrichtung mit Prioritätsvorgabe
DE10062995A1 (de) * 2000-12-16 2002-07-11 Micronas Gmbh Unterbrecher-Steuereinrichtung
US20030204655A1 (en) * 2002-04-24 2003-10-30 Schmisseur Mark A. Prioritizing vector generation in interrupt controllers
US7739438B2 (en) * 2003-02-12 2010-06-15 Hewlett-Packard Development Company, L.P. Method for priority-encoding interrupts and vectoring to interrupt code
GB2403822B (en) * 2003-07-07 2006-05-10 Advanced Risc Mach Ltd Data processing apparatus and method for handling interrupts
US7426728B2 (en) * 2003-09-24 2008-09-16 Hewlett-Packard Development, L.P. Reducing latency, when accessing task priority levels
US7590982B1 (en) * 2003-12-17 2009-09-15 Vmware, Inc. System and method for virtualizing processor and interrupt priorities
DE10361364B4 (de) * 2003-12-29 2010-07-01 Advanced Micro Devices, Inc., Sunnyvale Vorrichtung zum Behandeln von Interruptereignissen, mit der pegel-sensitive bzw. level-sensitive Interruptanforderungen in flankengetriggerten Interruptnachrichten umgesetzt werden
JP4241462B2 (ja) * 2004-03-26 2009-03-18 株式会社デンソー 制御ユニットおよびマイクロコンピュータ
US8127098B1 (en) * 2004-05-11 2012-02-28 Globalfoundries Inc. Virtualization of real mode execution
US20070016906A1 (en) * 2005-07-18 2007-01-18 Mistletoe Technologies, Inc. Efficient hardware allocation of processes to processors
JP4068106B2 (ja) * 2005-08-05 2008-03-26 三菱電機株式会社 リアルタイム組込み簡易モニタプログラム
EP2108147B1 (de) * 2006-10-20 2017-03-08 Her Majesty The Queen, In Right Of Canada As Represented By The Minister Of Health Through The Public Health Agency Of Canada Verfahren und vorrichtung zur softwarerichtlinienverwaltung
WO2008046218A1 (en) * 2006-10-20 2008-04-24 Her Majesty The Queen, In Right Of Canada As Represented By The Minister Of Health Through The Public Health Agency Of Canada Method and apparatus for creating a configurable browser-based forms application
US9946668B1 (en) * 2007-01-10 2018-04-17 The Mathworks, Inc. Automatic prioritization of interrupts in a modeling environment
CN101426099B (zh) * 2007-10-31 2010-08-25 晨星半导体股份有限公司 数字电视系统及数字电视中处理数据信号的方法
US20120226842A1 (en) * 2011-03-02 2012-09-06 Research In Motion Limited, an Ontario, Canada corporation Enhanced prioritising and unifying interrupt controller
US9952990B2 (en) * 2015-06-27 2018-04-24 Vmware, Inc. Implementing pseudo non-masking interrupts behavior using a priority interrupt controller
US9952895B2 (en) * 2015-06-27 2018-04-24 Vmware, Inc. Implementing pseudo non-masking interrupts behavior using a priority interrupt controller
CN110221861B (zh) * 2019-05-31 2023-08-29 常州市常河电子技术开发有限公司 一种cpu寄存器体系结构及其中断处理方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4365294A (en) * 1980-04-10 1982-12-21 Nizdorf Computer Corporation Modular terminal system using a common bus
US4604683A (en) 1984-12-10 1986-08-05 Advanced Computer Communications Communication controller using multiported random access memory
GB9012950D0 (en) * 1989-11-03 1990-08-01 Ibm Programmable interrupt controller
WO1993000638A1 (en) 1991-06-26 1993-01-07 Ast Research, Inc. Automatic distribution of interrupts controller for a multiple processor computer system
US5384724A (en) * 1991-09-05 1995-01-24 Texas Instruments Incorporated Electronic circuit and method for half adder logic
EP0545581B1 (de) 1991-12-06 1999-04-21 National Semiconductor Corporation Integriertes Datenverarbeitungssystem mit CPU-Kern und unabhängigem parallelen, digitalen Signalprozessormodul
JPH0713772A (ja) * 1993-06-29 1995-01-17 Mitsubishi Electric Corp データ処理装置
JPH0721035A (ja) * 1993-07-02 1995-01-24 Mitsubishi Denki Eng Kk データ処理装置

Also Published As

Publication number Publication date
WO1999034298A1 (en) 1999-07-08
EP1049985B1 (de) 2008-02-27
AU2012599A (en) 1999-07-19
EP1049985A1 (de) 2000-11-08
CN1328677C (zh) 2007-07-25
DE69839194T2 (de) 2009-03-26
EP1049985A4 (de) 2001-12-19
CN1286775A (zh) 2001-03-07
WO1999034298A9 (en) 1999-10-28
US6298410B1 (en) 2001-10-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806