DE69739718D1 - Verfahren und gerät zum wiedereinsetzen von basisregisterset - Google Patents

Verfahren und gerät zum wiedereinsetzen von basisregisterset

Info

Publication number
DE69739718D1
DE69739718D1 DE69739718T DE69739718T DE69739718D1 DE 69739718 D1 DE69739718 D1 DE 69739718D1 DE 69739718 T DE69739718 T DE 69739718T DE 69739718 T DE69739718 T DE 69739718T DE 69739718 D1 DE69739718 D1 DE 69739718D1
Authority
DE
Germany
Prior art keywords
register set
establishing basis
establishing
basis register
basis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69739718T
Other languages
English (en)
Inventor
Dale C Morris
Jack D Mills
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idea Corp USA
Original Assignee
Idea Corp USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Idea Corp USA filed Critical Idea Corp USA
Application granted granted Critical
Publication of DE69739718D1 publication Critical patent/DE69739718D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
DE69739718T 1996-10-03 1997-09-26 Verfahren und gerät zum wiedereinsetzen von basisregisterset Expired - Lifetime DE69739718D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/725,573 US5859999A (en) 1996-10-03 1996-10-03 System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
PCT/US1997/017369 WO1998014866A1 (en) 1996-10-03 1997-09-26 Method and apparatus for restoring a predicate register set

Publications (1)

Publication Number Publication Date
DE69739718D1 true DE69739718D1 (de) 2010-02-04

Family

ID=24915094

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69739718T Expired - Lifetime DE69739718D1 (de) 1996-10-03 1997-09-26 Verfahren und gerät zum wiedereinsetzen von basisregisterset

Country Status (6)

Country Link
US (1) US5859999A (de)
EP (1) EP1010064B1 (de)
JP (1) JP3771273B2 (de)
AU (1) AU4802197A (de)
DE (1) DE69739718D1 (de)
WO (1) WO1998014866A1 (de)

Families Citing this family (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6148350A (en) * 1998-05-29 2000-11-14 3Com Corporation System for allocating an integer unit of memory greater than a requested size and filling the extra space due to difference in sizes with extraneous data
US6115808A (en) * 1998-12-30 2000-09-05 Intel Corporation Method and apparatus for performing predicate hazard detection
US20040158695A1 (en) 1999-05-03 2004-08-12 Laurent Ugen Method and apparatus for handling transfer of guarded instructions in a computer system
US6640315B1 (en) 1999-06-26 2003-10-28 Board Of Trustees Of The University Of Illinois Method and apparatus for enhancing instruction level parallelism
US6539503B1 (en) 1999-11-23 2003-03-25 Hewlett-Packard Company Method and apparatus for testing error detection
US6681322B1 (en) 1999-11-26 2004-01-20 Hewlett-Packard Development Company L.P. Method and apparatus for emulating an instruction set extension in a digital computer system
US6668315B1 (en) 1999-11-26 2003-12-23 Hewlett-Packard Development Company, L.P. Methods and apparatus for exchanging the contents of registers
US6388489B1 (en) 1999-11-26 2002-05-14 Hewlett-Packard Company Large input function replaying dynamic entry latch with static and monotonic dual rail outputs
US6651176B1 (en) * 1999-12-08 2003-11-18 Hewlett-Packard Development Company, L.P. Systems and methods for variable control of power dissipation in a pipelined processor
US6678853B1 (en) 1999-12-17 2004-01-13 Hewlett-Packard Development Company, L.P. Method and apparatus for generating random code
US6625714B1 (en) * 1999-12-17 2003-09-23 Hewlett-Packard Development Company, L.P. Parallel distributed function translation lookaside buffer
US6470437B1 (en) * 1999-12-17 2002-10-22 Hewlett-Packard Company Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design
US6622284B1 (en) 1999-12-17 2003-09-16 Hewlett-Packard Development Company, L.P. Method and apparatus for detection of errors in one-hot words
US6493812B1 (en) 1999-12-17 2002-12-10 Hewlett-Packard Company Apparatus and method for virtual address aliasing and multiple page size support in a computer system having a prevalidated cache
US6484238B1 (en) 1999-12-20 2002-11-19 Hewlett-Packard Company Apparatus and method for detecting snoop hits on victim lines issued to a higher level cache
US6535989B1 (en) 1999-12-22 2003-03-18 Hewlett-Packard Company Input clock delayed by a plurality of elements that are connected to logic circuitry to produce a clock frequency having a rational multiple less than one
US7171547B1 (en) * 1999-12-28 2007-01-30 Intel Corporation Method and apparatus to save processor architectural state for later process resumption
US6591360B1 (en) 2000-01-18 2003-07-08 Hewlett-Packard Development Company Local stall/hazard detect in superscalar, pipelined microprocessor
US6587940B1 (en) 2000-01-18 2003-07-01 Hewlett-Packard Development Company Local stall/hazard detect in superscalar, pipelined microprocessor to avoid re-read of register file
US6622238B1 (en) 2000-01-24 2003-09-16 Hewlett-Packard Development Company, L.P. System and method for providing predicate data
US6438681B1 (en) 2000-01-24 2002-08-20 Hewlett-Packard Company Detection of data hazards between instructions by decoding register indentifiers in each stage of processing system pipeline and comparing asserted bits in the decoded register indentifiers
US6604192B1 (en) 2000-01-24 2003-08-05 Hewlett-Packard Development Company, L.P. System and method for utilizing instruction attributes to detect data hazards
US6643762B1 (en) 2000-01-24 2003-11-04 Hewlett-Packard Development Company, L.P. Processing system and method utilizing a scoreboard to detect data hazards between instructions of computer programs
US6715060B1 (en) 2000-01-28 2004-03-30 Hewlett-Packard Development Company, L.P. Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data
US6512706B1 (en) 2000-01-28 2003-01-28 Hewlett-Packard Company System and method for writing to a register file
US6490674B1 (en) 2000-01-28 2002-12-03 Hewlett-Packard Company System and method for coalescing data utilized to detect data hazards
US6643800B1 (en) * 2000-02-02 2003-11-04 Hewlett-Packard Development Company, L.P. Method and apparatus for testing microarchitectural features by using tests written in microcode
US6618801B1 (en) * 2000-02-02 2003-09-09 Hewlett-Packard Development Company, L.P. Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information
US6820190B1 (en) 2000-02-02 2004-11-16 Hewlett-Packard Development Company, L.P. Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructions
US6487550B1 (en) 2000-02-03 2002-11-26 Hewlett-Packard Company Method and apparatus for finding a first element
US6895420B1 (en) 2000-02-16 2005-05-17 Hewlett-Packard Development Company, L.P. Apparatus and method for sharing data FET for a four-way multiplexer
US6292041B1 (en) 2000-02-16 2001-09-18 Hewlett Packard Company Circuit and method for limiting subthreshold leakage
US6560737B1 (en) 2000-02-16 2003-05-06 Hewlett-Packard Development Company, L.P. Method for adding scan controllability and observability to domino CMOS with low area and delay overhead
US6317379B1 (en) 2000-02-18 2001-11-13 Hewlett-Packard Company Determine output of a read/write port
US6789186B1 (en) 2000-02-18 2004-09-07 Hewlett-Packard Development Company, L.P. Method and apparatus to reduce penalty of microcode lookup
US6532580B1 (en) 2000-02-18 2003-03-11 Hewlett-Packard Company In-place method for inserting repeater buffers in an integrated circuit
US6704820B1 (en) 2000-02-18 2004-03-09 Hewlett-Packard Development Company, L.P. Unified cache port consolidation
US6560664B1 (en) 2000-02-18 2003-05-06 Hewlett Packard Development Company, L.P. Method and apparatus for translation lookaside buffers to access a common hardware page walker
US6587964B1 (en) 2000-02-18 2003-07-01 Hewlett-Packard Development Company, L.P. Transparent software emulation as an alternative to hardware bus lock
US6804769B1 (en) 2000-02-18 2004-10-12 Hewlett-Packard Development Company, L.P. Unified buffer for tracking disparate long-latency operations in a microprocessor
DE10050589B4 (de) 2000-02-18 2006-04-06 Hewlett-Packard Development Co., L.P., Houston Vorrichtung und Verfahren zur Verwendung beim Durchführen einer Gleitkomma-Multiplizier-Akkumulier-Operation
US6397375B1 (en) 2000-02-18 2002-05-28 Hewlett-Packard Company Method for managing metal resources for over-the-block routing in integrated circuits
US6477690B1 (en) 2000-02-18 2002-11-05 Hewlett-Packard Company In-place repeater insertion methodology for over-the-block routed integrated circuits
US6636928B1 (en) 2000-02-18 2003-10-21 Hewlett-Packard Development Company, L.P. Write posting with global ordering in multi-path systems
US6625759B1 (en) 2000-02-18 2003-09-23 Hewlett-Packard Development Company, L.P. Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit
US6745322B1 (en) 2000-02-18 2004-06-01 Hewlett-Packard Development Company, Lp. Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition
US6654712B1 (en) 2000-02-18 2003-11-25 Hewlett-Packard Development Company, L.P. Method to reduce skew in clock signal distribution using balanced wire widths
US6629167B1 (en) 2000-02-18 2003-09-30 Hewlett-Packard Development Company, L.P. Pipeline decoupling buffer for handling early data and late data
US6542862B1 (en) 2000-02-18 2003-04-01 Hewlett-Packard Development Company, L.P. Determining register dependency in multiple architecture systems
US6807625B1 (en) 2000-02-18 2004-10-19 Hewlett-Packard Development Company, L.P. Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions
US6910122B1 (en) * 2000-02-18 2005-06-21 Hewlett-Packard Development Company, L.P. Method and apparatus for preserving pipeline data during a pipeline stall and for recovering from the pipeline stall
US6728823B1 (en) 2000-02-18 2004-04-27 Hewlett-Packard Development Company, L.P. Cache connection with bypassing feature
US6654849B1 (en) 2000-02-18 2003-11-25 Hewlett-Packard Development Company, L.P. Method and apparatus to minimize additional address bits and loading when adding a small patch RAM to a microcode ROM
US6622241B1 (en) 2000-02-18 2003-09-16 Hewlett-Packard Development Company, L.P. Method and apparatus for reducing branch prediction table pollution
US6591393B1 (en) 2000-02-18 2003-07-08 Hewlett-Packard Development Company, L.P. Masking error detection/correction latency in multilevel cache transfers
US6711671B1 (en) 2000-02-18 2004-03-23 Hewlett-Packard Development Company, L.P. Non-speculative instruction fetch in speculative processing
US6490656B1 (en) 2000-02-18 2002-12-03 Hewlett-Packard Company Retaining state information of an array of elements by subdividing the array into groups of elements
US6609247B1 (en) * 2000-02-18 2003-08-19 Hewlett-Packard Development Company Method and apparatus for re-creating the trace of an emulated instruction set when executed on hardware native to a different instruction set field
US6408426B1 (en) 2000-02-19 2002-06-18 Hewlett-Packard Company Method for determining locations of interconnect repeater farms during physical design of integrated circuits
US6470438B1 (en) 2000-02-22 2002-10-22 Hewlett-Packard Company Methods and apparatus for reducing false hits in a non-tagged, n-way cache
US6721875B1 (en) * 2000-02-22 2004-04-13 Hewlett-Packard Development Company, L.P. Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form
US6351796B1 (en) 2000-02-22 2002-02-26 Hewlett-Packard Company Methods and apparatus for increasing the efficiency of a higher level cache by selectively performing writes to the higher level cache
US6606720B1 (en) 2000-02-22 2003-08-12 Hewlett-Packard Development Company Scan structure for CMOS storage elements
GB2363480B (en) * 2000-06-13 2002-05-08 Siroyan Ltd Predicated execution of instructions in processors
US6658471B1 (en) * 2000-06-29 2003-12-02 International Business Machines Corporation Method and system for zero overhead software performance measurement instrumentation
US6516388B1 (en) 2000-09-15 2003-02-04 Hewlett-Packard Company Method and apparatus for reducing cache pollution
US6826681B2 (en) * 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US20030088761A1 (en) * 2001-11-02 2003-05-08 Paver Nigel C. Register context usage indicator
US20030126414A1 (en) * 2002-01-02 2003-07-03 Grochowski Edward T. Processing partial register writes in an out-of order processor
US7143270B1 (en) 2004-01-30 2006-11-28 Hewlett-Packard Development Company, L.P. System and method for adding an instruction to an instruction set architecture
JP4159586B2 (ja) * 2006-08-03 2008-10-01 エヌイーシーコンピュータテクノ株式会社 情報処理装置および情報処理の高速化方法
US8131982B2 (en) * 2008-06-13 2012-03-06 International Business Machines Corporation Branch prediction instructions having mask values involving unloading and loading branch history data
US10338923B2 (en) * 2009-05-05 2019-07-02 International Business Machines Corporation Branch prediction path wrong guess instruction
US8819399B1 (en) * 2009-07-31 2014-08-26 Google Inc. Predicated control flow and store instructions for native code module security
US10360039B2 (en) * 2009-09-28 2019-07-23 Nvidia Corporation Predicted instruction execution in parallel processors with reduced per-thread state information including choosing a minimum or maximum of two operands based on a predicate value
US8521999B2 (en) * 2010-03-11 2013-08-27 International Business Machines Corporation Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history
EP2689325B1 (de) 2011-03-25 2018-01-17 NXP USA, Inc. Prozessorsystem mit eigenschaftsregister, computersystem, verfahren zur verwaltung von eigenschaften und computerprogrammprodukt
CN107239260B (zh) * 2017-05-11 2020-07-24 中国电子科技集团公司第三十八研究所 一种面向数字信号处理器的多谓词控制及编译优化方法
US11106466B2 (en) 2018-06-18 2021-08-31 International Business Machines Corporation Decoupling of conditional branches
US11907713B2 (en) * 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029126B2 (ja) * 1977-01-14 1985-07-09 株式会社日立製作所 デ−タ処理装置
US4445173A (en) * 1981-09-11 1984-04-24 Data General Corporation Improved system for saving and restoring state in call and return operations
US4821231A (en) * 1983-04-18 1989-04-11 Motorola, Inc. Method and apparatus for selectively evaluating an effective address for a coprocessor
US5321823A (en) * 1988-07-20 1994-06-14 Digital Equipment Corporation Digital processor with bit mask for counting registers for fast register saves
US5416911A (en) * 1993-02-02 1995-05-16 International Business Machines Corporation Performance enhancement for load multiple register instruction
DE69506623T2 (de) * 1994-06-03 1999-07-22 Motorola Inc Datenprozessor mit einer Ausführungseinheit zur Durchführung von Ladebefehlen und Verfahren zu seinem Betrieb
US5694565A (en) * 1995-09-11 1997-12-02 International Business Machines Corporation Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions

Also Published As

Publication number Publication date
EP1010064B1 (de) 2009-12-23
JP2001501759A (ja) 2001-02-06
US5859999A (en) 1999-01-12
WO1998014866A1 (en) 1998-04-09
EP1010064A1 (de) 2000-06-21
EP1010064A4 (de) 2006-07-26
AU4802197A (en) 1998-04-24
JP3771273B2 (ja) 2006-04-26

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