DE69837775D1 - Dynamische logische Schaltung und selbstgetaktetes Pipeline-Datenwegsystem - Google Patents

Dynamische logische Schaltung und selbstgetaktetes Pipeline-Datenwegsystem

Info

Publication number
DE69837775D1
DE69837775D1 DE69837775T DE69837775T DE69837775D1 DE 69837775 D1 DE69837775 D1 DE 69837775D1 DE 69837775 T DE69837775 T DE 69837775T DE 69837775 T DE69837775 T DE 69837775T DE 69837775 D1 DE69837775 D1 DE 69837775D1
Authority
DE
Germany
Prior art keywords
self
logic circuit
data path
path system
dynamic logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69837775T
Other languages
English (en)
Other versions
DE69837775T2 (de
Inventor
Koji Fujii
Takakuni Douseki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE69837775D1 publication Critical patent/DE69837775D1/de
Application granted granted Critical
Publication of DE69837775T2 publication Critical patent/DE69837775T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0966—Self-timed logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
DE69837775T 1997-03-03 1998-03-02 Dynamische logische Schaltung und selbstgetaktetes Pipeline-Datenwegsystem Expired - Lifetime DE69837775T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6173597 1997-03-03
JP06173597A JP3451579B2 (ja) 1997-03-03 1997-03-03 自己同期型パイプラインデータパス回路

Publications (2)

Publication Number Publication Date
DE69837775D1 true DE69837775D1 (de) 2007-06-28
DE69837775T2 DE69837775T2 (de) 2008-01-31

Family

ID=13179762

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69837775T Expired - Lifetime DE69837775T2 (de) 1997-03-03 1998-03-02 Dynamische logische Schaltung und selbstgetaktetes Pipeline-Datenwegsystem

Country Status (4)

Country Link
US (1) US6225827B1 (de)
EP (1) EP0863614B1 (de)
JP (1) JP3451579B2 (de)
DE (1) DE69837775T2 (de)

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EP1028434A1 (de) * 1999-02-11 2000-08-16 Infineon Technologies North America Corp. Dynamische logische schaltung
US6262615B1 (en) 1999-02-25 2001-07-17 Infineon Technologies Ag Dynamic logic circuit
US6356117B1 (en) * 2000-09-29 2002-03-12 Sun Microsystems, Inc. Asynchronously controlling data transfers within a circuit
US6492838B2 (en) * 2001-04-11 2002-12-10 Hewlett-Packard Company System and method for improving performance of dynamic circuits
US6907534B2 (en) * 2001-06-29 2005-06-14 Hewlett-Packard Development Company, L.P. Minimizing power consumption in pipelined circuit by shutting down pipelined circuit in response to predetermined period of time having expired
DE10162309A1 (de) * 2001-12-19 2003-07-03 Philips Intellectual Property Verfahren und Anordnung zur Erhöhung der Sicherheit von Schaltkreisen gegen unbefugten Zugriff
GB0210625D0 (en) * 2002-05-09 2002-06-19 Paradigm Design Systems Control of guard flops
US6744282B1 (en) * 2003-03-27 2004-06-01 International Business Machines Corporation Latching dynamic logic structure, and integrated circuit including same
US7375402B2 (en) * 2004-07-07 2008-05-20 Semi Solutions, Llc Method and apparatus for increasing stability of MOS memory cells
US7224205B2 (en) * 2004-07-07 2007-05-29 Semi Solutions, Llc Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors
US8247840B2 (en) * 2004-07-07 2012-08-21 Semi Solutions, Llc Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode
US7683433B2 (en) * 2004-07-07 2010-03-23 Semi Solution, Llc Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors
US7651905B2 (en) * 2005-01-12 2010-01-26 Semi Solutions, Llc Apparatus and method for reducing gate leakage in deep sub-micron MOS transistors using semi-rectifying contacts
US7898297B2 (en) * 2005-01-04 2011-03-01 Semi Solution, Llc Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits
JP2007019811A (ja) * 2005-07-07 2007-01-25 Oki Electric Ind Co Ltd ドミノｃｍｏｓ論理回路
US7863689B2 (en) * 2006-09-19 2011-01-04 Semi Solutions, Llc. Apparatus for using a well current source to effect a dynamic threshold voltage of a MOS transistor
US8805678B2 (en) * 2006-11-09 2014-08-12 Broadcom Corporation Method and system for asynchronous pipeline architecture for multiple independent dual/stereo channel PCM processing
US8207784B2 (en) * 2008-02-12 2012-06-26 Semi Solutions, Llc Method and apparatus for MOSFET drain-source leakage reduction
US7746109B1 (en) 2009-04-02 2010-06-29 Xilinx, Inc. Circuits for sharing self-timed logic
US7746101B1 (en) 2009-04-02 2010-06-29 Xilinx, Inc. Cascading input structure for logic blocks in integrated circuits
US8527572B1 (en) 2009-04-02 2013-09-03 Xilinx, Inc. Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same
US7746108B1 (en) 2009-04-02 2010-06-29 Xilinx, Inc. Compute-centric architecture for integrated circuits
US9002915B1 (en) 2009-04-02 2015-04-07 Xilinx, Inc. Circuits for shifting bussed data
US8706793B1 (en) 2009-04-02 2014-04-22 Xilinx, Inc. Multiplier circuits with optional shift function
US7982496B1 (en) 2009-04-02 2011-07-19 Xilinx, Inc. Bus-based logic blocks with optional constant input
US9411554B1 (en) 2009-04-02 2016-08-09 Xilinx, Inc. Signed multiplier circuit utilizing a uniform array of logic blocks
US7733123B1 (en) * 2009-04-02 2010-06-08 Xilinx, Inc. Implementing conditional statements in self-timed logic circuits
US7948265B1 (en) 2009-04-02 2011-05-24 Xilinx, Inc. Circuits for replicating self-timed logic
US7977972B2 (en) 2009-08-07 2011-07-12 The Board Of Trustees Of The University Of Arkansas Ultra-low power multi-threshold asynchronous circuit design
US8402164B1 (en) 2010-10-27 2013-03-19 Xilinx, Inc. Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit
KR101911060B1 (ko) * 2012-03-19 2018-10-23 삼성전자주식회사 푸터가 없는 ｎｐ 도미노 로직 회로와 이를 포함하는 장치들
US8836372B1 (en) 2013-03-01 2014-09-16 Raytheon Company Minimizing power consumption in asynchronous dataflow architectures
US9281820B2 (en) * 2013-03-01 2016-03-08 Raytheon Company Minimizing power consumption in asynchronous dataflow architectures
US9094013B2 (en) * 2013-05-24 2015-07-28 The Board Of Trustees Of The University Of Arkansas Single component sleep-convention logic (SCL) modules
CN113472323B (zh) * 2021-08-11 2023-06-23 安徽大学 一种强锁存结构的d触发器电路

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435658A (en) * 1981-02-17 1984-03-06 Burroughs Corporation Two-level threshold circuitry for large scale integrated circuit memories
US4859873A (en) * 1987-07-17 1989-08-22 Western Digital Corporation CMOS Schmitt trigger with independently biased high/low threshold circuits
US5486774A (en) * 1991-11-26 1996-01-23 Nippon Telegraph And Telephone Corporation CMOS logic circuits having low and high-threshold voltage transistors
JP3277089B2 (ja) * 1995-02-14 2002-04-22 株式会社東芝 乗算器及び積和演算装置
US5821769A (en) * 1995-04-21 1998-10-13 Nippon Telegraph And Telephone Corporation Low voltage CMOS logic circuit with threshold voltage control
JP3192086B2 (ja) * 1996-04-25 2001-07-23 日本電気株式会社 半導体集積回路
US5831451A (en) * 1996-07-19 1998-11-03 Texas Instruments Incorporated Dynamic logic circuits using transistors having differing threshold voltages

Also Published As

Publication number Publication date
US6225827B1 (en) 2001-05-01
JP3451579B2 (ja) 2003-09-29
EP0863614A2 (de) 1998-09-09
EP0863614B1 (de) 2007-05-16
EP0863614A3 (de) 1999-09-08
JPH10247848A (ja) 1998-09-14
DE69837775T2 (de) 2008-01-31

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Legal Events

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