DE69836786D1 - Speicherschnittstellenvorrichtung und Vorrichtung zur Speicheradressengeneration - Google Patents

Speicherschnittstellenvorrichtung und Vorrichtung zur Speicheradressengeneration

Info

Publication number
DE69836786D1
DE69836786D1 DE69836786T DE69836786T DE69836786D1 DE 69836786 D1 DE69836786 D1 DE 69836786D1 DE 69836786 T DE69836786 T DE 69836786T DE 69836786 T DE69836786 T DE 69836786T DE 69836786 D1 DE69836786 D1 DE 69836786D1
Authority
DE
Germany
Prior art keywords
memory
address generation
generation device
interface device
memory address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69836786T
Other languages
English (en)
Other versions
DE69836786T2 (de
Inventor
Yoichiro Miki
Masahiro Tani
Kazuki Ninomiya
Naoya Tokunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Texas Instruments Inc
Original Assignee
Matsushita Electric Industrial Co Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP27175197A external-priority patent/JP3343207B2/ja
Priority claimed from JP35852897A external-priority patent/JP3455405B2/ja
Application filed by Matsushita Electric Industrial Co Ltd, Texas Instruments Inc filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69836786D1 publication Critical patent/DE69836786D1/de
Application granted granted Critical
Publication of DE69836786T2 publication Critical patent/DE69836786T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Dram (AREA)
  • Image Input (AREA)
  • Information Transfer Systems (AREA)
DE69836786T 1997-10-03 1998-10-02 Speicherschnittstellenvorrichtung und Vorrichtung zur Speicheradressengeneration Expired - Lifetime DE69836786T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP27175197A JP3343207B2 (ja) 1997-10-03 1997-10-03 メモリインターフェース装置
JP27175197 1997-10-03
JP35852897 1997-12-25
JP35852897A JP3455405B2 (ja) 1997-12-25 1997-12-25 メモリアドレス発生装置

Publications (2)

Publication Number Publication Date
DE69836786D1 true DE69836786D1 (de) 2007-02-15
DE69836786T2 DE69836786T2 (de) 2007-04-26

Family

ID=26549857

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69836786T Expired - Lifetime DE69836786T2 (de) 1997-10-03 1998-10-02 Speicherschnittstellenvorrichtung und Vorrichtung zur Speicheradressengeneration

Country Status (3)

Country Link
US (2) US6453394B2 (de)
EP (2) EP0908827B8 (de)
DE (1) DE69836786T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6301299B1 (en) 1994-10-28 2001-10-09 Matsushita Electric Industrial Co., Ltd. Memory controller for an ATSC video decoder
WO2002027426A2 (en) * 2000-09-01 2002-04-04 Op40, Inc. System, method, uses, products, program products, and business methods for distributed internet and distributed network services
US6915360B2 (en) * 2001-04-06 2005-07-05 Texas Instruments Incorporated Cell buffering system with priority cache in an ATM system
US20040257856A1 (en) * 2003-06-23 2004-12-23 Texas Instruments Incorporated Dual-port functionality for a single-port cell memory device
CN100411436C (zh) * 2003-08-18 2008-08-13 联发科技股份有限公司 存储已解码宏块运动向量的存储器使用方法
US7302379B2 (en) * 2003-12-07 2007-11-27 Adaptive Spectrum And Signal Alignment, Inc. DSL system estimation and parameter recommendation
JP4765260B2 (ja) * 2004-03-31 2011-09-07 日本電気株式会社 データ処理装置およびその処理方法ならびにプログラムおよび携帯電話装置
US8156276B2 (en) * 2005-08-01 2012-04-10 Ati Technologies Ulc Method and apparatus for data transfer
US20070204076A1 (en) * 2006-02-28 2007-08-30 Agere Systems Inc. Method and apparatus for burst transfer
US8218770B2 (en) * 2005-09-13 2012-07-10 Agere Systems Inc. Method and apparatus for secure key management and protection
US7912060B1 (en) 2006-03-20 2011-03-22 Agere Systems Inc. Protocol accelerator and method of using same
US7599364B2 (en) * 2005-09-13 2009-10-06 Agere Systems Inc. Configurable network connection address forming hardware
US7610444B2 (en) * 2005-09-13 2009-10-27 Agere Systems Inc. Method and apparatus for disk address and transfer size management
US8521955B2 (en) 2005-09-13 2013-08-27 Lsi Corporation Aligned data storage for network attached media streaming systems
US7461214B2 (en) * 2005-11-15 2008-12-02 Agere Systems Inc. Method and system for accessing a single port memory
TWI325274B (en) * 2006-10-12 2010-05-21 Ind Tech Res Inst Method for mapping memory addresses, memory accessing apparatus and method thereof
TWI627860B (zh) * 2016-05-31 2018-06-21 晨星半導體股份有限公司 影音處理裝置與方法
CN108647154A (zh) * 2018-05-14 2018-10-12 国网山东省电力公司阳谷县供电公司 一种在集中器中进行参数修改的方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1228677A (en) * 1984-06-21 1987-10-27 Cray Research, Inc. Peripheral interface system
US4884069A (en) * 1987-03-19 1989-11-28 Apple Computer, Inc. Video apparatus employing VRAMs
US5247627A (en) * 1987-06-05 1993-09-21 Mitsubishi Denki Kabushiki Kaisha Digital signal processor with conditional branch decision unit and storage of conditional branch decision results
US5163132A (en) * 1987-09-24 1992-11-10 Ncr Corporation Integrated controller using alternately filled and emptied buffers for controlling bi-directional data transfer between a processor and a data storage device
JPH0664834B2 (ja) * 1987-12-16 1994-08-22 三洋電機株式会社 逆転音声再生回路
US5724540A (en) * 1988-03-28 1998-03-03 Hitachi, Ltd. Memory system having a column address counter and a page address counter
DE69016509T2 (de) * 1989-05-31 1995-06-01 Fujitsu Ltd Integrierte Halbleiterschaltungsanordnung mit Testschaltung.
US5204953A (en) * 1989-08-04 1993-04-20 Intel Corporation One clock address pipelining in segmentation unit
JPH03180933A (ja) * 1989-12-08 1991-08-06 Matsushita Electric Ind Co Ltd スタックメモリ
CA2080210C (en) * 1992-01-02 1998-10-27 Nader Amini Bidirectional data storage facility for bus interface unit
JPH06332843A (ja) * 1992-06-24 1994-12-02 Seiko Epson Corp 動画映像データ転送装置およびコンピュータシステム
JP3419046B2 (ja) * 1993-09-27 2003-06-23 セイコーエプソン株式会社 映像表示装置
US5546347A (en) * 1994-07-22 1996-08-13 Integrated Device Technology, Inc. Interleaving architecture and method for a high density FIFO
US5905729A (en) * 1995-07-19 1999-05-18 Fujitsu Network Communications, Inc. Mapping a data cell in a communication switch
JPH0955869A (ja) 1995-08-14 1997-02-25 Sony Corp 画像同期化装置および方法
US5822776A (en) * 1996-03-11 1998-10-13 Mitel Corporation Multiplexed random access memory with time division multiplexing through a single read/write port
US5909704A (en) * 1997-01-09 1999-06-01 Raytheon Company High speed address generator
JPH10326342A (ja) 1997-05-27 1998-12-08 Canon Inc メモリ制御回路
US5909225A (en) * 1997-05-30 1999-06-01 Hewlett-Packard Co. Frame buffer cache for graphics applications
JP3037220B2 (ja) * 1997-09-03 2000-04-24 日本電気アイシーマイコンシステム株式会社 グラフィック処理装置およびその処理方法
US6145033A (en) * 1998-07-17 2000-11-07 Seiko Epson Corporation Management of display FIFO requests for DRAM access wherein low priority requests are initiated when FIFO level is below/equal to high threshold value

Also Published As

Publication number Publication date
US6732252B2 (en) 2004-05-04
DE69836786T2 (de) 2007-04-26
US20020184464A1 (en) 2002-12-05
US20010056526A1 (en) 2001-12-27
US6453394B2 (en) 2002-09-17
EP0908827A2 (de) 1999-04-14
EP1691296A3 (de) 2010-03-17
EP0908827A3 (de) 2000-05-03
EP0908827B8 (de) 2007-05-09
EP0908827B1 (de) 2007-01-03
EP1691296A2 (de) 2006-08-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

Owner name: TEXAS INSTRUMENTS INC., DALLAS, TEX., US