DE69832575T2 - Anordnung zur Überprüfung der Signaltaktgenauigkeit in einer digitalen Testeinrichtung - Google Patents

Anordnung zur Überprüfung der Signaltaktgenauigkeit in einer digitalen Testeinrichtung Download PDF

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Publication number
DE69832575T2
DE69832575T2 DE69832575T DE69832575T DE69832575T2 DE 69832575 T2 DE69832575 T2 DE 69832575T2 DE 69832575 T DE69832575 T DE 69832575T DE 69832575 T DE69832575 T DE 69832575T DE 69832575 T2 DE69832575 T2 DE 69832575T2
Authority
DE
Germany
Prior art keywords
checking
arrangement
test device
signal timing
digital test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69832575T
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English (en)
Other versions
DE69832575D1 (de
Inventor
William R Lawrence
David H Armstrong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of DE69832575D1 publication Critical patent/DE69832575D1/de
Application granted granted Critical
Publication of DE69832575T2 publication Critical patent/DE69832575T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31903Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE69832575T 1997-11-26 1998-09-14 Anordnung zur Überprüfung der Signaltaktgenauigkeit in einer digitalen Testeinrichtung Expired - Fee Related DE69832575T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/979,529 US6192496B1 (en) 1997-11-26 1997-11-26 System for verifying signal timing accuracy on a digital testing device

Publications (2)

Publication Number Publication Date
DE69832575D1 DE69832575D1 (de) 2006-01-05
DE69832575T2 true DE69832575T2 (de) 2006-06-14

Family

ID=25526951

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69832575T Expired - Fee Related DE69832575T2 (de) 1997-11-26 1998-09-14 Anordnung zur Überprüfung der Signaltaktgenauigkeit in einer digitalen Testeinrichtung

Country Status (4)

Country Link
US (1) US6192496B1 (de)
EP (1) EP0919823B1 (de)
JP (1) JPH11271406A (de)
DE (1) DE69832575T2 (de)

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US6397158B1 (en) * 1999-04-29 2002-05-28 Sun Microsystems, Inc. Method for determining capacitance values for quieting noisy power conductors
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US6724209B1 (en) 2000-04-13 2004-04-20 Ralph G. Whitten Method for testing signal paths between an integrated circuit wafer and a wafer tester
US6622103B1 (en) 2000-06-20 2003-09-16 Formfactor, Inc. System for calibrating timing of an integrated circuit wafer tester
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US6570397B2 (en) * 2001-08-07 2003-05-27 Agilent Technologies, Inc. Timing calibration and timing calibration verification of electronic circuit testers
US6825693B2 (en) * 2002-12-31 2004-11-30 Intel Corporation Remote receiver detection
US7206981B2 (en) * 2002-12-31 2007-04-17 Intel Corporation Compliance testing through test equipment
US6906549B2 (en) 2002-12-31 2005-06-14 Intel Corporation Asynchronous coupling and decoupling of chips
US7096155B2 (en) * 2003-03-03 2006-08-22 Dell Products L.P. Method, system and apparatus for providing real-time led status of embedded controllers to system management software
US6847203B1 (en) * 2003-07-02 2005-01-25 International Business Machines Corporation Applying parametric test patterns for high pin count ASICs on low pin count testers
US7154259B2 (en) * 2003-10-23 2006-12-26 Formfactor, Inc. Isolation buffers with controlled equal time delays
US7673197B2 (en) * 2003-11-20 2010-03-02 Practical Engineering Inc. Polymorphic automatic test systems and methods
US7106081B2 (en) * 2004-07-08 2006-09-12 Verigy Ipco Parallel calibration system for a test device
DE102004052246B3 (de) * 2004-10-27 2006-06-14 Infineon Technologies Ag Halbleiterbauelement, Anordnung und Verfahren zur Charakterisierung eines Prüfgerätes für Halbleiterbauelemente
US7281181B2 (en) * 2005-06-27 2007-10-09 Verigy (Singapore) Pte. Ltd. Systems, methods and computer programs for calibrating an automated circuit test system
KR20070012597A (ko) * 2005-07-23 2007-01-26 삼성전자주식회사 시스템 보드 검사 장치 및 방법
US20070186131A1 (en) * 2006-02-06 2007-08-09 Texas Instruments Incorporated Low cost imbedded load board diagnostic test fixture
US7502974B2 (en) * 2006-02-22 2009-03-10 Verigy (Singapore) Pte. Ltd. Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets
WO2008051107A1 (en) * 2006-10-26 2008-05-02 Motorola Inc. Testing of a test element
US7930452B1 (en) * 2007-06-05 2011-04-19 Cisco Technology, Inc. Parallel link electrical and timing parameter specification for output driver and input receiver that selects bandwidth or frequency based on timing parameters
US7716004B2 (en) * 2007-07-02 2010-05-11 Advanced Micro Devices, Inc. Method and apparatus for matching test equipment calibration
KR101414980B1 (ko) * 2008-06-30 2014-07-09 삼성전자주식회사 테스트 시스템
US7924035B2 (en) 2008-07-15 2011-04-12 Formfactor, Inc. Probe card assembly for electronic device testing with DC test resource sharing
US7783938B1 (en) * 2008-07-31 2010-08-24 Keithly Instruments, Inc. Result directed diagnostic method and system
US8692538B2 (en) * 2011-06-09 2014-04-08 Teradyne, Inc. Test equipment calibration
US9921263B2 (en) * 2013-03-31 2018-03-20 Ziota Technology Inc. Electronic identification slave connector
US10345355B2 (en) 2013-03-31 2019-07-09 Ziota Technology Inc. Method of communication between distributed wire harness test units using wire under test
FR3005525B1 (fr) * 2013-05-07 2015-04-24 Labinal Gaine de protection d'un harnais electrique afin de prevenir sa deterioration
KR102055335B1 (ko) 2013-08-21 2020-01-22 삼성전자주식회사 테스트 장치 및 이를 포함하는 테스트 시스템
US10162002B2 (en) 2015-07-20 2018-12-25 International Business Machines Corporation Tuning a testing apparatus for measuring skew
US10684319B2 (en) * 2015-07-20 2020-06-16 International Business Machines Corporation Tuning a testing apparatus for measuring skew
CN105510663B (zh) * 2015-11-27 2018-10-02 中国电子科技集团公司第五十八研究所 一种应用于高幅值差分信号的自动化采集测试方法
DE102016202021B3 (de) * 2016-02-10 2017-03-23 Bender Gmbh & Co. Kg Verfahren und Vorrichtungen zur Erkennung einer Unterbrechung einer Schutzleiterverbindung
JP2019133457A (ja) * 2018-01-31 2019-08-08 オムロン株式会社 制御装置及び制御方法
US11604219B2 (en) * 2020-12-15 2023-03-14 Teradyne, Inc. Automatic test equipement having fiber optic connections to remote servers

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US5083083A (en) * 1986-09-19 1992-01-21 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US4827437A (en) * 1986-09-22 1989-05-02 Vhl Associates, Inc. Auto calibration circuit for VLSI tester
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US5212443A (en) * 1990-09-05 1993-05-18 Schlumberger Technologies, Inc. Event sequencer for automatic test equipment
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US5504432A (en) 1993-08-31 1996-04-02 Hewlett-Packard Company System and method for detecting short, opens and connected pins on a printed circuit board using automatic test equipment
US5390194A (en) 1993-11-17 1995-02-14 Grumman Aerospace Corporation ATG test station
US5633596A (en) 1994-01-11 1997-05-27 Key Solutions Ltd. Fixtureless automatic test equipment and a method for registration for use therewith
US5485096A (en) 1994-04-05 1996-01-16 Aksu; Allen Printed circuit board tester having a test bed with spring probes and easily replaceable switch cards
US5471145A (en) 1994-04-07 1995-11-28 Texas Instruments Incorporated Calibrating transition dependent timing errors in automatic test equipment using a precise pulse width generator
US5539305A (en) * 1994-10-03 1996-07-23 Botka; Julius K. Calibration board for an electronic circuit tester
US5590136A (en) 1995-01-25 1996-12-31 Hewlett-Packard Co Method for creating an in-circuit test for an electronic device
US6025708A (en) * 1997-11-26 2000-02-15 Hewlett Packard Company System for verifying signal voltage level accuracy on a digital testing device

Also Published As

Publication number Publication date
JPH11271406A (ja) 1999-10-08
EP0919823A3 (de) 2003-10-15
DE69832575D1 (de) 2006-01-05
EP0919823A2 (de) 1999-06-02
US6192496B1 (en) 2001-02-20
EP0919823B1 (de) 2005-11-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US

8328 Change in the person/name/address of the agent

Representative=s name: DILG HAEUSLER SCHINDELMANN PATENTANWALTSGESELLSCHA

8327 Change in the person/name/address of the patent owner

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE., SG

8339 Ceased/non-payment of the annual fee