DE69826233D1 - Verfahren zur Herstellung eines SOI-Substrates - Google Patents

Verfahren zur Herstellung eines SOI-Substrates

Info

Publication number
DE69826233D1
DE69826233D1 DE69826233T DE69826233T DE69826233D1 DE 69826233 D1 DE69826233 D1 DE 69826233D1 DE 69826233 T DE69826233 T DE 69826233T DE 69826233 T DE69826233 T DE 69826233T DE 69826233 D1 DE69826233 D1 DE 69826233D1
Authority
DE
Germany
Prior art keywords
production
soi substrate
soi
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69826233T
Other languages
English (en)
Other versions
DE69826233T2 (de
Inventor
Flavio Villa
Gabriele Barlocchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69826233D1 publication Critical patent/DE69826233D1/de
Application granted granted Critical
Publication of DE69826233T2 publication Critical patent/DE69826233T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
DE69826233T 1998-01-13 1998-01-13 Verfahren zur Herstellung eines SOI-Substrates Expired - Fee Related DE69826233T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19980830007 EP0929095B1 (de) 1998-01-13 1998-01-13 Verfahren zur Herstellung eines SOI-Substrates

Publications (2)

Publication Number Publication Date
DE69826233D1 true DE69826233D1 (de) 2004-10-21
DE69826233T2 DE69826233T2 (de) 2005-10-20

Family

ID=8236516

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69826233T Expired - Fee Related DE69826233T2 (de) 1998-01-13 1998-01-13 Verfahren zur Herstellung eines SOI-Substrates

Country Status (2)

Country Link
EP (1) EP0929095B1 (de)
DE (1) DE69826233T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69937106T2 (de) * 1999-07-09 2008-06-05 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Herstellung von Strukturen mit vergrabenen Oxidbereichen in einem Halbleitersubstrat
EP1073112A1 (de) 1999-07-26 2001-01-31 STMicroelectronics S.r.l. Verfahren zur Herstellung eines SOI-Wafers mittels Oxidierung von vergrabenen Hohlräumen
EP1326272A1 (de) * 2001-12-28 2003-07-09 STMicroelectronics S.r.l. Verfahren zur Herstellung von SOI-Strukturen
EP2552040A1 (de) 2011-07-29 2013-01-30 Alcatel Lucent Verfahren und Vorrichtung zur Leitweglenkung und Bandbreitenzuweisung in einer optischen Wellenlängenmultiplexübertragung

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760036A (en) * 1987-06-15 1988-07-26 Delco Electronics Corporation Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation
US5115289A (en) * 1988-11-21 1992-05-19 Hitachi, Ltd. Semiconductor device and semiconductor memory device
US4948456A (en) * 1989-06-09 1990-08-14 Delco Electronics Corporation Confined lateral selective epitaxial growth
JPH0697400A (ja) * 1990-11-29 1994-04-08 Texas Instr Inc <Ti> Ｓｏｉウェーハ及びその製造方法
US5208167A (en) * 1991-09-30 1993-05-04 Rohm Co., Ltd. Method for producing SOI substrate
US5635411A (en) * 1991-11-12 1997-06-03 Rohm Co., Ltd. Method of making semiconductor apparatus
JP3153632B2 (ja) * 1992-06-11 2001-04-09 ローム株式会社 Ｓｏｉ構造の製造方法

Also Published As

Publication number Publication date
EP0929095B1 (de) 2004-09-15
EP0929095A1 (de) 1999-07-14
DE69826233T2 (de) 2005-10-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee