DE69815590D1 - Anordnung von zwei Speichern auf der selben monolitischen integrierten Schaltung - Google Patents

Anordnung von zwei Speichern auf der selben monolitischen integrierten Schaltung

Info

Publication number
DE69815590D1
DE69815590D1 DE69815590T DE69815590T DE69815590D1 DE 69815590 D1 DE69815590 D1 DE 69815590D1 DE 69815590 T DE69815590 T DE 69815590T DE 69815590 T DE69815590 T DE 69815590T DE 69815590 D1 DE69815590 D1 DE 69815590D1
Authority
DE
Germany
Prior art keywords
memories
arrangement
integrated circuit
monolithic integrated
same monolithic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69815590T
Other languages
English (en)
Inventor
Alessandro Brigati
Jean Devin
Bruno Leconte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE69815590D1 publication Critical patent/DE69815590D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Storage Device Security (AREA)
  • Memory System (AREA)
DE69815590T 1997-04-08 1998-03-20 Anordnung von zwei Speichern auf der selben monolitischen integrierten Schaltung Expired - Lifetime DE69815590D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9704285A FR2761802B1 (fr) 1997-04-08 1997-04-08 Ensemble de deux memoires sur un meme circuit integre monolithique

Publications (1)

Publication Number Publication Date
DE69815590D1 true DE69815590D1 (de) 2003-07-24

Family

ID=9505647

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69815590T Expired - Lifetime DE69815590D1 (de) 1997-04-08 1998-03-20 Anordnung von zwei Speichern auf der selben monolitischen integrierten Schaltung

Country Status (5)

Country Link
US (3) US6205512B1 (de)
EP (1) EP0875899B1 (de)
JP (1) JPH113596A (de)
DE (1) DE69815590D1 (de)
FR (1) FR2761802B1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2761802B1 (fr) * 1997-04-08 1999-06-18 Sgs Thomson Microelectronics Ensemble de deux memoires sur un meme circuit integre monolithique
US6804136B2 (en) * 2002-06-21 2004-10-12 Micron Technology, Inc. Write once read only memory employing charge trapping in insulators
US7017017B2 (en) * 2002-11-08 2006-03-21 Intel Corporation Memory controllers with interleaved mirrored memory modes
US6882590B2 (en) * 2003-01-29 2005-04-19 Micron Technology, Inc. Multiple configuration multiple chip memory device and method
US8108588B2 (en) * 2003-04-16 2012-01-31 Sandisk Il Ltd. Monolithic read-while-write flash memory device
US7162551B2 (en) * 2003-10-31 2007-01-09 Lucent Technologies Inc. Memory management system having a linked list processor
US7159049B2 (en) * 2003-10-31 2007-01-02 Lucent Technologies Inc. Memory management system including on access flow regulator for a data processing system

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667190A (en) * 1982-07-30 1987-05-19 Honeywell Inc. Two axis fast access memory
JPS60200287A (ja) * 1984-03-24 1985-10-09 株式会社東芝 記憶装置
US4924427A (en) * 1985-11-15 1990-05-08 Unisys Corporation Direct memory access controller with direct memory to memory transfers
US4908502A (en) 1988-02-08 1990-03-13 Pitney Bowes Inc. Fault tolerant smart card
US5335336A (en) * 1988-03-28 1994-08-02 Hitachi, Ltd. Memory device having refresh mode returning previous page address for resumed page mode
DE69021666D1 (de) * 1989-08-02 1995-09-21 Fujitsu Ltd Abtastwandlerregelkreis mit Speichern und Adressengenerator zur Erzeugung eines den Speichern zugeführten Zickzackadressensignals.
JPH0511827A (ja) * 1990-04-23 1993-01-22 Canon Inc 工業用自動装置の実行時間出力方式
JPH04233642A (ja) * 1990-07-27 1992-08-21 Dell Usa Corp キャッシュアクセスと並列的にメモリアクセスを行なうプロセッサ及びそれに用いられる方法
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
US5349578A (en) * 1991-05-10 1994-09-20 Nec Corporation Time slot switching function diagnostic system
US5615355A (en) * 1992-10-22 1997-03-25 Ampex Corporation Method and apparatus for buffering a user application from the timing requirements of a DRAM
US5455912A (en) * 1993-06-18 1995-10-03 Vtech Industries, Inc. High speed/low overhead bus arbitration apparatus and method for arbitrating a system bus
US6154850A (en) * 1993-11-01 2000-11-28 Beaufort River, Inc. Data storage system and method
CA2221797C (en) * 1995-05-26 2000-08-22 Emulex Corporation Linked caches for context data search
US5724501A (en) * 1996-03-29 1998-03-03 Emc Corporation Quick recovery of write cache in a fault tolerant I/O system
US5802561A (en) * 1996-06-28 1998-09-01 Digital Equipment Corporation Simultaneous, mirror write cache
US5774135A (en) * 1996-11-05 1998-06-30 Vlsi, Technology, Inc. Non-contiguous memory location addressing scheme
FR2761802B1 (fr) * 1997-04-08 1999-06-18 Sgs Thomson Microelectronics Ensemble de deux memoires sur un meme circuit integre monolithique
US6052133A (en) * 1997-06-27 2000-04-18 S3 Incorporated Multi-function controller and method for a computer graphics display system
US5962930A (en) * 1997-11-26 1999-10-05 Intel Corporation Method and apparatus for detecting supply power loss

Also Published As

Publication number Publication date
JPH113596A (ja) 1999-01-06
EP0875899A1 (de) 1998-11-04
US20010001206A1 (en) 2001-05-17
US20010000815A1 (en) 2001-05-03
US6205512B1 (en) 2001-03-20
US6279068B2 (en) 2001-08-21
FR2761802A1 (fr) 1998-10-09
EP0875899B1 (de) 2003-06-18
FR2761802B1 (fr) 1999-06-18
US6434056B2 (en) 2002-08-13

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Legal Events

Date Code Title Description
8332 No legal effect for de