DE69803873T2 - Steuerungsvorrichtung zum verteilten speicherzugriff - Google Patents

Steuerungsvorrichtung zum verteilten speicherzugriff

Info

Publication number
DE69803873T2
DE69803873T2 DE69803873T DE69803873T DE69803873T2 DE 69803873 T2 DE69803873 T2 DE 69803873T2 DE 69803873 T DE69803873 T DE 69803873T DE 69803873 T DE69803873 T DE 69803873T DE 69803873 T2 DE69803873 T2 DE 69803873T2
Authority
DE
Germany
Prior art keywords
control device
memory access
distributed memory
distributed
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69803873T
Other languages
English (en)
Other versions
DE69803873D1 (de
Inventor
Robert Stoye
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Conexant Systems UK Ltd
Original Assignee
Virata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Virata Ltd filed Critical Virata Ltd
Publication of DE69803873D1 publication Critical patent/DE69803873D1/de
Application granted granted Critical
Publication of DE69803873T2 publication Critical patent/DE69803873T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
DE69803873T 1997-11-13 1998-11-11 Steuerungsvorrichtung zum verteilten speicherzugriff Expired - Fee Related DE69803873T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9724028.7A GB9724028D0 (en) 1997-11-13 1997-11-13 Shared memory access controller
PCT/GB1998/003372 WO1999026154A1 (en) 1997-11-13 1998-11-11 Shared memory access controller

Publications (2)

Publication Number Publication Date
DE69803873D1 DE69803873D1 (de) 2002-03-21
DE69803873T2 true DE69803873T2 (de) 2002-08-22

Family

ID=10822037

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69803873T Expired - Fee Related DE69803873T2 (de) 1997-11-13 1998-11-11 Steuerungsvorrichtung zum verteilten speicherzugriff

Country Status (7)

Country Link
US (1) US6754899B1 (de)
EP (1) EP1029284B1 (de)
AU (1) AU1044899A (de)
DE (1) DE69803873T2 (de)
GB (1) GB9724028D0 (de)
IL (1) IL133020A0 (de)
WO (1) WO1999026154A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1059587B1 (de) 1999-06-09 2007-04-18 Texas Instruments Incorporated Host-Zugriff zu gemeinschaftlichem Speicher mit Hochprioritätsbetriebsart
JP3755415B2 (ja) * 2001-04-04 2006-03-15 株式会社デンソー 処理実行装置、当該処理実行装置に搭載される処理プログラム、及び記録媒体
FR2825167A1 (fr) * 2001-05-22 2002-11-29 Koninkl Philips Electronics Nv Procede et systeme d'acces a une memoire commune
TW594487B (en) * 2003-01-30 2004-06-21 Via Tech Inc System chip and related method of data access
US20050144401A1 (en) * 2003-12-30 2005-06-30 Pantalone Brett A. Multiprocessor mobile terminal with shared memory arbitration
KR100652690B1 (ko) * 2004-10-28 2006-12-07 엘지전자 주식회사 이동 통신 단말기의 멀티 프로세서 장치
US20060294412A1 (en) * 2005-06-27 2006-12-28 Dell Products L.P. System and method for prioritizing disk access for shared-disk applications
JP6519258B2 (ja) * 2015-03-23 2019-05-29 株式会社バッファロー 情報処理装置、及び情報処理方法
CN111444024B (zh) * 2020-04-13 2024-04-12 维沃移动通信有限公司 请求响应方法、电子设备及存储介质
US11606346B2 (en) 2020-06-29 2023-03-14 Rockwell Automation Technologies, Inc. Method and apparatus for managing reception of secure data packets
US11599649B2 (en) * 2020-06-29 2023-03-07 Rockwell Automation Technologies, Inc. Method and apparatus for managing transmission of secure data packets

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798591A (en) 1971-09-28 1974-03-19 Gen Electric Co Ltd Access circuit for a time-shared data processing equipment
US4400771A (en) 1975-12-04 1983-08-23 Tokyo Shibaura Electric Co., Ltd. Multi-processor system with programmable memory-access priority control
US4059851A (en) * 1976-07-12 1977-11-22 Ncr Corporation Priority network for devices coupled by a common bus
US4493036A (en) 1982-12-14 1985-01-08 Honeywell Information Systems Inc. Priority resolver having dynamically adjustable priority levels
IT1206331B (it) * 1983-10-25 1989-04-14 Honeywell Inf Systems Architettura di sistema di elaborazione dati.
US4829467A (en) 1984-12-21 1989-05-09 Canon Kabushiki Kaisha Memory controller including a priority order determination circuit
US5088053A (en) * 1987-11-16 1992-02-11 Intel Corporation Memory controller as for a video signal processor
DE3923872A1 (de) * 1989-07-19 1991-01-24 Philips Patentverwaltung Schaltungsanordnung zum steuern des zugriffs auf einen speicher
CA2065979C (en) * 1991-06-10 1999-01-19 Stephen Patrick Thompson Mode dependent minimum fifo fill level controls processor access to video memory
US5546548A (en) * 1993-03-31 1996-08-13 Intel Corporation Arbiter and arbitration process for a dynamic and flexible prioritization
WO1997005550A1 (en) * 1995-07-27 1997-02-13 Intel Corporation Protocol for arbitrating access to a shared memory area using historical state information

Also Published As

Publication number Publication date
EP1029284B1 (de) 2002-02-13
US6754899B1 (en) 2004-06-22
DE69803873D1 (de) 2002-03-21
GB9724028D0 (en) 1998-01-14
AU1044899A (en) 1999-06-07
EP1029284A1 (de) 2000-08-23
WO1999026154A1 (en) 1999-05-27
IL133020A0 (en) 2001-03-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee