DE69733444D1 - Datenprozessor mit variabler Anzahl von Pipelinestufen - Google Patents

Datenprozessor mit variabler Anzahl von Pipelinestufen

Info

Publication number
DE69733444D1
DE69733444D1 DE69733444T DE69733444T DE69733444D1 DE 69733444 D1 DE69733444 D1 DE 69733444D1 DE 69733444 T DE69733444 T DE 69733444T DE 69733444 T DE69733444 T DE 69733444T DE 69733444 D1 DE69733444 D1 DE 69733444D1
Authority
DE
Germany
Prior art keywords
data processor
variable number
pipeline stages
pipeline
stages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69733444T
Other languages
English (en)
Inventor
Masato Suzuki
Toru Morikawa
Nobuo Higaki
Shinya Miyaji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69733444D1 publication Critical patent/DE69733444D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3873—Variable length pipelines, e.g. elastic pipeline
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Power Sources (AREA)
  • Multi Processors (AREA)
DE69733444T 1996-03-29 1997-03-26 Datenprozessor mit variabler Anzahl von Pipelinestufen Expired - Lifetime DE69733444D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7731396 1996-03-29

Publications (1)

Publication Number Publication Date
DE69733444D1 true DE69733444D1 (de) 2005-07-14

Family

ID=13630438

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69733444T Expired - Lifetime DE69733444D1 (de) 1996-03-29 1997-03-26 Datenprozessor mit variabler Anzahl von Pipelinestufen

Country Status (6)

Country Link
US (1) US6018796A (de)
EP (1) EP0798633B1 (de)
KR (1) KR100471794B1 (de)
CN (2) CN1183462C (de)
DE (1) DE69733444D1 (de)
TW (1) TW337567B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6167529A (en) * 1997-12-30 2000-12-26 Intel Corporation Instruction dependent clock scheme
JP2001092662A (ja) * 1999-09-22 2001-04-06 Toshiba Corp プロセッサコア及びこれを用いたプロセッサ
US6862677B1 (en) * 2000-02-16 2005-03-01 Koninklijke Philips Electronics N.V. System and method for eliminating write back to register using dead field indicator
US7024663B2 (en) * 2002-07-10 2006-04-04 Micron Technology, Inc. Method and system for generating object code to facilitate predictive memory retrieval
US20040243875A1 (en) * 2002-12-23 2004-12-02 Vishram Dalvi Instruction dependent clock scheme
KR20070004705A (ko) * 2004-03-10 2007-01-09 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 전자 회로와 그 동작 방법
JP4444860B2 (ja) 2005-03-10 2010-03-31 富士通株式会社 リコンフィギュラブル回路およびそのコンフィギュレーション方法
CN100451951C (zh) * 2006-01-26 2009-01-14 深圳艾科创新微电子有限公司 Risc cpu中的5+3级流水线设计方法
US7809926B2 (en) * 2006-11-03 2010-10-05 Cornell Research Foundation, Inc. Systems and methods for reconfiguring on-chip multiprocessors
US20110067015A1 (en) * 2008-02-15 2011-03-17 Masamichi Takagi Program parallelization apparatus, program parallelization method, and program parallelization program
JP5481793B2 (ja) * 2008-03-21 2014-04-23 富士通株式会社 演算処理装置および同装置の制御方法
JP5170234B2 (ja) * 2008-03-25 2013-03-27 富士通株式会社 マルチプロセッサ
US11645083B2 (en) * 2013-08-23 2023-05-09 Texas Instruments Incorporated Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency
CN105739948A (zh) * 2014-12-12 2016-07-06 超威半导体(上海)有限公司 自适应可调节的流水线以及适应性地调节流水线的方法
KR102171119B1 (ko) 2015-11-05 2020-10-28 삼성전자주식회사 복수개의 블록 기반의 파이프라인을 이용한 데이터 처리 속도 개선 장치 및 그 동작 방법
CN109634667B (zh) * 2018-12-11 2023-03-14 中国电子科技集团公司第四十七研究所 一种基于时钟的双速流水线架构微处理器及其实现方法
CN110045989B (zh) * 2019-03-14 2023-11-14 合肥雷芯智能科技有限公司 一种动态切换式低功耗处理器
CN110780616A (zh) * 2019-09-06 2020-02-11 重庆东渝中能实业有限公司 一种基于流水线技术处理通讯命令的方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57168350A (en) * 1981-04-09 1982-10-16 Mitsubishi Electric Corp Information processor
JPS58106641A (ja) * 1981-12-18 1983-06-25 Fujitsu Ltd パイプライン命令実行制御方式
JP2806524B2 (ja) * 1988-03-04 1998-09-30 日本電気株式会社 ベクトル演算命令発行制御方法
JPH02159624A (ja) * 1988-12-13 1990-06-19 Nec Corp 先入れ先出しレジスタ装置
JPH077356B2 (ja) * 1989-05-19 1995-01-30 株式会社東芝 パイプライン方式のマイクロプロセッサ
US5488729A (en) * 1991-05-15 1996-01-30 Ross Technology, Inc. Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
US5471626A (en) * 1992-05-06 1995-11-28 International Business Machines Corporation Variable stage entry/exit instruction pipeline
US5706459A (en) * 1994-01-06 1998-01-06 Fujitsu Limited Processor having a variable number of stages in a pipeline
SG75756A1 (en) * 1994-02-28 2000-10-24 Intel Corp Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path
US5778250A (en) * 1994-05-23 1998-07-07 Cirrus Logic, Inc. Method and apparatus for dynamically adjusting the number of stages of a multiple stage pipeline
US5734598A (en) * 1994-12-28 1998-03-31 Quantum Corporation Low power filter coefficient adaptation circuit for digital adaptive filter

Also Published As

Publication number Publication date
CN1183462C (zh) 2005-01-05
EP0798633B1 (de) 2005-06-08
KR970066864A (ko) 1997-10-13
CN1170906A (zh) 1998-01-21
EP0798633A2 (de) 1997-10-01
CN1303524C (zh) 2007-03-07
CN1607499A (zh) 2005-04-20
KR100471794B1 (ko) 2005-05-16
EP0798633A3 (de) 2000-01-26
US6018796A (en) 2000-01-25
TW337567B (en) 1998-08-01

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Legal Events

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