DE69724965D1 - Verfahren zur vereinfachung der herstellung eines dielektrischen zwischenschicht-stapels - Google Patents

Verfahren zur vereinfachung der herstellung eines dielektrischen zwischenschicht-stapels

Info

Publication number
DE69724965D1
DE69724965D1 DE69724965T DE69724965T DE69724965D1 DE 69724965 D1 DE69724965 D1 DE 69724965D1 DE 69724965 T DE69724965 T DE 69724965T DE 69724965 T DE69724965 T DE 69724965T DE 69724965 D1 DE69724965 D1 DE 69724965D1
Authority
DE
Germany
Prior art keywords
simplifying
production
dielectric interlayer
interlayer stack
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69724965T
Other languages
English (en)
Other versions
DE69724965T2 (de
Inventor
Nick Kepler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69724965D1 publication Critical patent/DE69724965D1/de
Application granted granted Critical
Publication of DE69724965T2 publication Critical patent/DE69724965T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69724965T 1996-07-01 1997-03-07 Verfahren zur vereinfachung der herstellung eines dielektrischen zwischenschicht-stapels Expired - Lifetime DE69724965T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/673,005 US5795820A (en) 1996-07-01 1996-07-01 Method for simplifying the manufacture of an interlayer dielectric stack
US673005 1996-07-01
PCT/US1997/003552 WO1998000863A1 (en) 1996-07-01 1997-03-07 Method for simplifying the manufacture of an interlayer dielectric stack

Publications (2)

Publication Number Publication Date
DE69724965D1 true DE69724965D1 (de) 2003-10-23
DE69724965T2 DE69724965T2 (de) 2004-07-22

Family

ID=24700935

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69724965T Expired - Lifetime DE69724965T2 (de) 1996-07-01 1997-03-07 Verfahren zur vereinfachung der herstellung eines dielektrischen zwischenschicht-stapels

Country Status (4)

Country Link
US (1) US5795820A (de)
EP (1) EP0909461B1 (de)
DE (1) DE69724965T2 (de)
WO (1) WO1998000863A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6190966B1 (en) * 1997-03-25 2001-02-20 Vantis Corporation Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration
US5915198A (en) * 1997-04-28 1999-06-22 Vanguard International Semiconductor Corporation Contact process using taper contact etching and polycide step
US6492282B1 (en) * 1997-04-30 2002-12-10 Siemens Aktiengesellschaft Integrated circuits and manufacturing methods
US6133139A (en) 1997-10-08 2000-10-17 International Business Machines Corporation Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof
US5880030A (en) * 1997-11-25 1999-03-09 Intel Corporation Unlanded via structure and method for making same
JP3722610B2 (ja) * 1998-01-14 2005-11-30 株式会社リコー 半導体装置の製造方法
US6025255A (en) * 1998-06-25 2000-02-15 Vanguard International Semiconductor Corporation Two-step etching process for forming self-aligned contacts
JP2000077625A (ja) * 1998-08-31 2000-03-14 Hitachi Ltd 半導体集積回路装置の製造方法
US6426263B1 (en) * 2000-08-11 2002-07-30 Agere Systems Guardian Corp. Method for making a merged contact window in a transistor to electrically connect the gate to either the source or the drain
US6528374B2 (en) * 2001-02-05 2003-03-04 International Business Machines Corporation Method for forming dielectric stack without interfacial layer
US8329575B2 (en) * 2010-12-22 2012-12-11 Applied Materials, Inc. Fabrication of through-silicon vias on silicon wafers
US10388654B2 (en) * 2018-01-11 2019-08-20 Globalfoundries Inc. Methods of forming a gate-to-source/drain contact structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3685449D1 (de) * 1985-03-15 1992-07-02 Fairchild Semiconductor Corp., Cupertino, Calif., Us
DE68926017T2 (de) * 1988-10-28 1996-08-22 At & T Corp Integrierte Schaltungherstellung, unter Anwendung eines Niedrig-Temperatur-Verfahrens zur Herstellung von Silicid-Strukturen
US5250468A (en) * 1990-02-05 1993-10-05 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including interlaying insulating film
EP0523856A3 (en) * 1991-06-28 1993-03-17 Sgs-Thomson Microelectronics, Inc. Method of via formation for multilevel interconnect integrated circuits
JP2765478B2 (ja) * 1994-03-30 1998-06-18 日本電気株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP0909461B1 (de) 2003-09-17
US5795820A (en) 1998-08-18
WO1998000863A1 (en) 1998-01-08
EP0909461A1 (de) 1999-04-21
DE69724965T2 (de) 2004-07-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES, INC., GARAND CAYMAN, KY