DE69709889T2 - Überspannungsdetektionsschaltung zur auswahl der prüfbetriebsart - Google Patents

Überspannungsdetektionsschaltung zur auswahl der prüfbetriebsart

Info

Publication number
DE69709889T2
DE69709889T2 DE69709889T DE69709889T DE69709889T2 DE 69709889 T2 DE69709889 T2 DE 69709889T2 DE 69709889 T DE69709889 T DE 69709889T DE 69709889 T DE69709889 T DE 69709889T DE 69709889 T2 DE69709889 T2 DE 69709889T2
Authority
DE
Germany
Prior art keywords
supervoltage
selecting
detection circuit
test mode
overvoltage detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69709889T
Other languages
English (en)
Other versions
DE69709889D1 (de
Inventor
C Sher
A Merritt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of DE69709889D1 publication Critical patent/DE69709889D1/de
Publication of DE69709889T2 publication Critical patent/DE69709889T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Dc-Dc Converters (AREA)
DE69709889T 1996-10-21 1997-10-21 Überspannungsdetektionsschaltung zur auswahl der prüfbetriebsart Expired - Lifetime DE69709889T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/734,504 US5841714A (en) 1996-10-21 1996-10-21 Supervoltage circuit
PCT/US1997/018734 WO1998018134A1 (en) 1996-10-21 1997-10-21 Overvoltage detection circuit for test mode selection

Publications (2)

Publication Number Publication Date
DE69709889D1 DE69709889D1 (de) 2002-02-28
DE69709889T2 true DE69709889T2 (de) 2002-09-05

Family

ID=24951958

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69709889T Expired - Lifetime DE69709889T2 (de) 1996-10-21 1997-10-21 Überspannungsdetektionsschaltung zur auswahl der prüfbetriebsart

Country Status (8)

Country Link
US (1) US5841714A (de)
EP (1) EP0932904B1 (de)
JP (1) JP3413446B2 (de)
KR (1) KR100319029B1 (de)
AT (1) ATE211577T1 (de)
AU (1) AU4985697A (de)
DE (1) DE69709889T2 (de)
WO (1) WO1998018134A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5949725A (en) * 1997-08-20 1999-09-07 Micron Technology, Inc. Method and apparatus for reprogramming a supervoltage circuit
US6496027B1 (en) * 1997-08-21 2002-12-17 Micron Technology, Inc. System for testing integrated circuit devices
US6046944A (en) * 1998-01-28 2000-04-04 Sun Microsystems, Inc. Bias generator circuit for low voltage applications
US6043702A (en) * 1998-01-29 2000-03-28 Sun Microsystems, Inc. Dynamic biasing for overshoot and undershoot protection circuits
US6347381B1 (en) * 1998-10-30 2002-02-12 Stmicroelectronics, Inc. Test mode circuitry for electronic storage devices and the like
US6285243B1 (en) 2000-02-23 2001-09-04 Micron Technology, Inc. High-voltage charge pump circuit
DE102004015269B4 (de) * 2004-03-29 2008-03-27 Infineon Technologies Ag Integrierte Schaltung zur Ermittelung einer Spannung
US9424911B2 (en) * 2014-01-06 2016-08-23 Marvell World Trade Ltd. Method and apparatus for screening memory cells for disturb failures

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH081760B2 (ja) * 1987-11-17 1996-01-10 三菱電機株式会社 半導体記憶装置
EP0367115B1 (de) * 1988-10-31 1994-03-16 Fujitsu Limited Integrierte Schaltung mit einer Signaldiskriminierungsschaltung und Verfahren zu deren Prüfung
US5019772A (en) * 1989-05-23 1991-05-28 International Business Machines Corporation Test selection techniques
KR940004408B1 (ko) * 1991-08-23 1994-05-25 삼성전자 주식회사 반도체 메모리 장치의 자동 스트레스 모드 테스트장치
US5212442A (en) * 1992-03-20 1993-05-18 Micron Technology, Inc. Forced substrate test mode for packaged integrated circuits
JP2885597B2 (ja) * 1993-03-10 1999-04-26 株式会社東芝 半導体メモリ
JPH0773062A (ja) * 1993-06-29 1995-03-17 Fujitsu Ltd 半導体集積回路装置
US5467306A (en) * 1993-10-04 1995-11-14 Texas Instruments Incorporated Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms
US5493532A (en) * 1994-05-31 1996-02-20 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory with disabled edge transition pulse generation during special test mode
US5627485A (en) * 1995-06-26 1997-05-06 Micron Technology, Inc. Voltage-independent super voltage detection circuit

Also Published As

Publication number Publication date
AU4985697A (en) 1998-05-15
ATE211577T1 (de) 2002-01-15
JP3413446B2 (ja) 2003-06-03
EP0932904B1 (de) 2002-01-02
EP0932904A1 (de) 1999-08-04
US5841714A (en) 1998-11-24
KR100319029B1 (ko) 2002-01-05
JP2000504457A (ja) 2000-04-11
KR20000052681A (ko) 2000-08-25
WO1998018134A1 (en) 1998-04-30
DE69709889D1 (de) 2002-02-28

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