DE69629645D1 - Parallele Signalverarbeitungsschaltung - Google Patents
Parallele SignalverarbeitungsschaltungInfo
- Publication number
- DE69629645D1 DE69629645D1 DE69629645T DE69629645T DE69629645D1 DE 69629645 D1 DE69629645 D1 DE 69629645D1 DE 69629645 T DE69629645 T DE 69629645T DE 69629645 T DE69629645 T DE 69629645T DE 69629645 D1 DE69629645 D1 DE 69629645D1
- Authority
- DE
- Germany
- Prior art keywords
- signal processing
- processing circuit
- parallel signal
- parallel
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/42—Sequential comparisons in series-connected stages with no change in value of analogue signal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/15—Correlation function computation including computation of convolution operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06J—HYBRID COMPUTING ARRANGEMENTS
- G06J1/00—Hybrid computing arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/20—Analysis of motion
- G06T7/223—Analysis of motion using block-matching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
- H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
- H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/02—Indexing scheme relating to groups G06F7/02 - G06F7/026
- G06F2207/025—String search, i.e. pattern matching, e.g. find identical word or best match in a string
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/10—Image acquisition modality
- G06T2207/10016—Video; Image sequence
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Data Mining & Analysis (AREA)
- Databases & Information Systems (AREA)
- Multimedia (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Power Engineering (AREA)
- Algebra (AREA)
- Automation & Control Theory (AREA)
- Evolutionary Computation (AREA)
- Fuzzy Systems (AREA)
- Analogue/Digital Conversion (AREA)
- Dram (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28165695 | 1995-10-30 | ||
JP7281656A JPH09130685A (ja) | 1995-10-30 | 1995-10-30 | 半導体装置及びそれを用いた半導体回路、相関演算装置、信号処理システム |
JP8021659A JPH09200624A (ja) | 1996-01-16 | 1996-01-16 | 並列信号処理回路、信号処理装置および信号処理システム |
JP2165996 | 1996-01-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69629645D1 true DE69629645D1 (de) | 2003-10-02 |
DE69629645T2 DE69629645T2 (de) | 2004-06-17 |
Family
ID=26358757
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69629645T Expired - Fee Related DE69629645T2 (de) | 1995-10-30 | 1996-10-29 | Parallele Signalverarbeitungsschaltung |
Country Status (3)
Country | Link |
---|---|
US (1) | US5951632A (de) |
EP (3) | EP0772143B1 (de) |
DE (1) | DE69629645T2 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6281831B1 (en) * | 1997-05-15 | 2001-08-28 | Yozan Inc. | Analog to digital converter |
US7610326B2 (en) * | 2002-09-18 | 2009-10-27 | Canon Kabushiki Kaisha | Arithmetic circuit for calculating a cumulative value as a result of parallel arithmetic processing |
KR101498874B1 (ko) * | 2008-07-31 | 2015-03-05 | 조지아 테크 리서치 코포레이션 | 멀티-기가비트 아날로그 디지털 변환기 |
WO2013184735A2 (en) * | 2012-06-05 | 2013-12-12 | Venntis Llc | Microcontroller multiplexer processing |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2536922A1 (fr) * | 1982-11-26 | 1984-06-01 | Efcis | Comparateur logique a plusieurs fonctions |
US4654815A (en) * | 1985-02-07 | 1987-03-31 | Texas Instruments Incorporated | Analog signal conditioning and digitizing integrated circuit |
US4885757A (en) * | 1987-06-01 | 1989-12-05 | Texas Instruments Incorporated | Digital adaptive receiver employing maximum-likelihood sequence estimation with neural networks |
JP3055739B2 (ja) * | 1993-01-13 | 2000-06-26 | シャープ株式会社 | 乗算回路 |
US5565809A (en) * | 1993-09-20 | 1996-10-15 | Yozan Inc. | Computational circuit |
US5396442A (en) * | 1993-10-19 | 1995-03-07 | Yozan Inc. | Multiplication circuit for multiplying analog inputs by digital inputs |
JPH08125502A (ja) * | 1994-10-28 | 1996-05-17 | Canon Inc | 半導体装置とこれを用いた半導体回路、相関演算装置、a/d変換器、d/a変換器、及び信号処理システム |
JPH08204567A (ja) * | 1995-01-31 | 1996-08-09 | Canon Inc | 半導体装置とこれを用いた半導体回路、相関演算装置、a/d変換器、d/a変換器及び信号処理システム |
-
1996
- 1996-10-25 US US08/736,938 patent/US5951632A/en not_active Expired - Fee Related
- 1996-10-29 EP EP96117354A patent/EP0772143B1/de not_active Expired - Lifetime
- 1996-10-29 DE DE69629645T patent/DE69629645T2/de not_active Expired - Fee Related
- 1996-10-29 EP EP02018794A patent/EP1262903A3/de not_active Withdrawn
- 1996-10-29 EP EP02018790A patent/EP1265185A3/de not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
US5951632A (en) | 1999-09-14 |
EP0772143B1 (de) | 2003-08-27 |
EP1265185A2 (de) | 2002-12-11 |
EP0772143A3 (de) | 1997-07-23 |
EP1262903A3 (de) | 2004-04-21 |
EP0772143A2 (de) | 1997-05-07 |
EP1262903A2 (de) | 2002-12-04 |
DE69629645T2 (de) | 2004-06-17 |
EP1265185A3 (de) | 2004-04-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |