DE69624158D1 - Superskalarer Prozessor mit mehreren Registerblöcken und Erzeugung von spekulativen Antwortadressen - Google Patents
Superskalarer Prozessor mit mehreren Registerblöcken und Erzeugung von spekulativen AntwortadressenInfo
- Publication number
- DE69624158D1 DE69624158D1 DE69624158T DE69624158T DE69624158D1 DE 69624158 D1 DE69624158 D1 DE 69624158D1 DE 69624158 T DE69624158 T DE 69624158T DE 69624158 T DE69624158 T DE 69624158T DE 69624158 D1 DE69624158 D1 DE 69624158D1
- Authority
- DE
- Germany
- Prior art keywords
- program
- program flow
- flow change
- generation
- return
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30054—Unconditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
- G06F9/30127—Register windows
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
- G06F9/4486—Formation of subprogram jump address
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Multi Processors (AREA)
- Devices For Executing Special Programs (AREA)
- Advance Control (AREA)
- Air Transport Of Granular Materials (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US39828495A | 1995-03-03 | 1995-03-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69624158D1 true DE69624158D1 (de) | 2002-11-14 |
DE69624158T2 DE69624158T2 (de) | 2003-06-05 |
Family
ID=23574784
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69624158T Expired - Lifetime DE69624158T2 (de) | 1995-03-03 | 1996-03-01 | Superskalarer Prozessor mit mehreren Registerblöcken und Erzeugung von spekulativen Antwortadressen |
Country Status (4)
Country | Link |
---|---|
US (1) | US5896528A (de) |
EP (1) | EP0730221B1 (de) |
AT (1) | ATE225958T1 (de) |
DE (1) | DE69624158T2 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6446224B1 (en) | 1995-03-03 | 2002-09-03 | Fujitsu Limited | Method and apparatus for prioritizing and handling errors in a computer system |
US6012137A (en) * | 1997-05-30 | 2000-01-04 | Sony Corporation | Special purpose processor for digital audio/video decoding |
US6157999A (en) * | 1997-06-03 | 2000-12-05 | Motorola Inc. | Data processing system having a synchronizing link stack and method thereof |
US6115777A (en) * | 1998-04-21 | 2000-09-05 | Idea Corporation | LOADRS instruction and asynchronous context switch |
US6353881B1 (en) * | 1999-05-17 | 2002-03-05 | Sun Microsystems, Inc. | Supporting space-time dimensional program execution by selectively versioning memory updates |
US20040250054A1 (en) * | 2003-06-09 | 2004-12-09 | Stark Jared W. | Line prediction using return prediction information |
US7555633B1 (en) | 2003-11-03 | 2009-06-30 | Advanced Micro Devices, Inc. | Instruction cache prefetch based on trace cache eviction |
US8069336B2 (en) * | 2003-12-03 | 2011-11-29 | Globalfoundries Inc. | Transitioning from instruction cache to trace cache on label boundaries |
US7197630B1 (en) | 2004-04-12 | 2007-03-27 | Advanced Micro Devices, Inc. | Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation |
US8190863B2 (en) | 2004-07-02 | 2012-05-29 | Intel Corporation | Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction |
US7904789B1 (en) * | 2006-03-31 | 2011-03-08 | Guillermo Rozas | Techniques for detecting and correcting errors in a memory device |
US8935574B2 (en) | 2011-12-16 | 2015-01-13 | Advanced Micro Devices, Inc. | Correlating traces in a computing system |
US8832500B2 (en) | 2012-08-10 | 2014-09-09 | Advanced Micro Devices, Inc. | Multiple clock domain tracing |
US8959398B2 (en) | 2012-08-16 | 2015-02-17 | Advanced Micro Devices, Inc. | Multiple clock domain debug capability |
US9513924B2 (en) * | 2013-06-28 | 2016-12-06 | Globalfoundries Inc. | Predictor data structure for use in pipelined processing |
US9619230B2 (en) | 2013-06-28 | 2017-04-11 | International Business Machines Corporation | Predictive fetching and decoding for selected instructions |
US10534609B2 (en) | 2017-08-18 | 2020-01-14 | International Business Machines Corporation | Code-specific affiliated register prediction |
US10908911B2 (en) | 2017-08-18 | 2021-02-02 | International Business Machines Corporation | Predicting and storing a predicted target address in a plurality of selected locations |
US11150908B2 (en) | 2017-08-18 | 2021-10-19 | International Business Machines Corporation | Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence |
US10884747B2 (en) | 2017-08-18 | 2021-01-05 | International Business Machines Corporation | Prediction of an affiliated register |
US10884746B2 (en) | 2017-08-18 | 2021-01-05 | International Business Machines Corporation | Determining and predicting affiliated registers based on dynamic runtime control flow analysis |
US10884745B2 (en) | 2017-08-18 | 2021-01-05 | International Business Machines Corporation | Providing a predicted target address to multiple locations based on detecting an affiliated relationship |
US11150904B2 (en) | 2017-08-18 | 2021-10-19 | International Business Machines Corporation | Concurrent prediction of branch addresses and update of register contents |
US10719328B2 (en) | 2017-08-18 | 2020-07-21 | International Business Machines Corporation | Determining and predicting derived values used in register-indirect branching |
US10620955B2 (en) | 2017-09-19 | 2020-04-14 | International Business Machines Corporation | Predicting a table of contents pointer value responsive to branching to a subroutine |
US10705973B2 (en) | 2017-09-19 | 2020-07-07 | International Business Machines Corporation | Initializing a data structure for use in predicting table of contents pointer values |
US10725918B2 (en) | 2017-09-19 | 2020-07-28 | International Business Machines Corporation | Table of contents cache entry having a pointer for a range of addresses |
US11061575B2 (en) | 2017-09-19 | 2021-07-13 | International Business Machines Corporation | Read-only table of contents register |
US10884929B2 (en) | 2017-09-19 | 2021-01-05 | International Business Machines Corporation | Set table of contents (TOC) register instruction |
US10713050B2 (en) | 2017-09-19 | 2020-07-14 | International Business Machines Corporation | Replacing Table of Contents (TOC)-setting instructions in code with TOC predicting instructions |
US10896030B2 (en) | 2017-09-19 | 2021-01-19 | International Business Machines Corporation | Code generation relating to providing table of contents pointer values |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2545789B2 (ja) * | 1986-04-14 | 1996-10-23 | 株式会社日立製作所 | 情報処理装置 |
EP0310445A3 (de) * | 1987-10-02 | 1990-12-27 | COMPUTER CONSOLES INCORPORATED (a Delaware corporation) | Hochgeschwindigkeitsregisterblock mit sich überlappenden Feldern |
US4822061A (en) * | 1987-10-02 | 1989-04-18 | K-Line Industries, Inc. | Valve seal retainer |
US5193205A (en) * | 1988-03-01 | 1993-03-09 | Mitsubishi Denki Kabushiki Kaisha | Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address |
US5159680A (en) * | 1988-07-28 | 1992-10-27 | Sun Microsystems, Inc. | Risc processing unit which selectively isolates register windows by indicating usage of adjacent register windows in status register |
US5487156A (en) * | 1989-12-15 | 1996-01-23 | Popescu; Valeri | Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched |
US5179673A (en) * | 1989-12-18 | 1993-01-12 | Digital Equipment Corporation | Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline |
US5276882A (en) * | 1990-07-27 | 1994-01-04 | International Business Machines Corp. | Subroutine return through branch history table |
US5226142A (en) * | 1990-11-21 | 1993-07-06 | Ross Technology, Inc. | High performance register file with overlapping windows |
JP3182438B2 (ja) * | 1991-10-28 | 2001-07-03 | 株式会社日立製作所 | データプロセッサ |
US5313634A (en) * | 1992-07-28 | 1994-05-17 | International Business Machines Corporation | Computer system branch prediction of subroutine returns |
US5604877A (en) * | 1994-01-04 | 1997-02-18 | Intel Corporation | Method and apparatus for resolving return from subroutine instructions in a computer processor |
EP0676691A3 (de) * | 1994-04-06 | 1996-12-11 | Hewlett Packard Co | Vorrichtung zur Registersicherstellung und Umspeicherung in einem digitalen Rechner. |
US5655132A (en) * | 1994-08-08 | 1997-08-05 | Rockwell International Corporation | Register file with multi-tasking support |
-
1995
- 1995-09-01 US US08/522,845 patent/US5896528A/en not_active Expired - Lifetime
-
1996
- 1996-03-01 AT AT96103172T patent/ATE225958T1/de not_active IP Right Cessation
- 1996-03-01 DE DE69624158T patent/DE69624158T2/de not_active Expired - Lifetime
- 1996-03-01 EP EP96103172A patent/EP0730221B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5896528A (en) | 1999-04-20 |
DE69624158T2 (de) | 2003-06-05 |
EP0730221A3 (de) | 1997-05-14 |
EP0730221A2 (de) | 1996-09-04 |
EP0730221B1 (de) | 2002-10-09 |
ATE225958T1 (de) | 2002-10-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |