DE69623461D1 - Koordination von befehlsausgabe in einem parallelen befehlsverarbeitungssystem - Google Patents

Koordination von befehlsausgabe in einem parallelen befehlsverarbeitungssystem

Info

Publication number
DE69623461D1
DE69623461D1 DE69623461T DE69623461T DE69623461D1 DE 69623461 D1 DE69623461 D1 DE 69623461D1 DE 69623461 T DE69623461 T DE 69623461T DE 69623461 T DE69623461 T DE 69623461T DE 69623461 D1 DE69623461 D1 DE 69623461D1
Authority
DE
Germany
Prior art keywords
coordination
processing system
command
parallel
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69623461T
Other languages
English (en)
Other versions
DE69623461T2 (de
Inventor
Sunil Savkar
C Shebanow
W Shen
Farnad Sajjadian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69623461D1 publication Critical patent/DE69623461D1/de
Application granted granted Critical
Publication of DE69623461T2 publication Critical patent/DE69623461T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69623461T 1995-06-01 1996-05-31 Koordination von befehlsausgabe in einem parallelen befehlsverarbeitungssystem Expired - Lifetime DE69623461T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45704995A 1995-06-01 1995-06-01
PCT/US1996/008255 WO1996038783A1 (en) 1995-06-01 1996-05-31 Method and apparatus for rotating active instructions in a parallel data processor

Publications (2)

Publication Number Publication Date
DE69623461D1 true DE69623461D1 (de) 2002-10-10
DE69623461T2 DE69623461T2 (de) 2003-07-24

Family

ID=23815247

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69623461T Expired - Lifetime DE69623461T2 (de) 1995-06-01 1996-05-31 Koordination von befehlsausgabe in einem parallelen befehlsverarbeitungssystem

Country Status (5)

Country Link
US (1) US5838940A (de)
EP (1) EP0829045B1 (de)
JP (1) JP3597540B2 (de)
DE (1) DE69623461T2 (de)
WO (1) WO1996038783A1 (de)

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JPH1049369A (ja) * 1996-08-07 1998-02-20 Ricoh Co Ltd データ処理装置
US6334213B1 (en) * 1998-01-20 2001-12-25 Preview Systems Merging of separate executable computer programs to form a single executable computer program
US5974531A (en) * 1998-02-17 1999-10-26 Industrial Technology Research Institute Methods and systems of stack renaming for superscalar stack-based data processors
US6345286B1 (en) * 1998-10-30 2002-02-05 International Business Machines Corporation 6-to-3 carry-save adder
JP3554211B2 (ja) * 1998-12-17 2004-08-18 富士通株式会社 マイクロプログラムを用いた命令制御装置および方法
US6807624B1 (en) * 1998-12-17 2004-10-19 Fujitsu Limited Instruction control device and method therefor
US6665708B1 (en) 1999-11-12 2003-12-16 Telefonaktiebolaget Lm Ericsson (Publ) Coarse grained determination of data dependence between parallel executed jobs in an information processing system
US6345351B1 (en) 1999-11-12 2002-02-05 Telefonaktiebolaget Lm Ericsson(Publ) Maintenance of speculative state of parallel executed jobs in an information processing system
US6351802B1 (en) * 1999-12-03 2002-02-26 Intel Corporation Method and apparatus for constructing a pre-scheduled instruction cache
US6785714B1 (en) * 2000-09-28 2004-08-31 Microsoft Corporation System and method for employing slot level locking of a cache
US6826630B2 (en) * 2001-09-14 2004-11-30 Seagate Technology Llc Prioritizing commands in a data storage device
US7825935B1 (en) * 2001-11-30 2010-11-02 Nvidia Corporation System, method and computer program product for using textures as instructions for graphics processing
US20070186081A1 (en) * 2006-02-06 2007-08-09 Shailender Chaudhry Supporting out-of-order issue in an execute-ahead processor
US20080077777A1 (en) * 2006-09-25 2008-03-27 Arm Limited Register renaming for instructions having unresolved condition codes
US8806505B1 (en) * 2008-06-30 2014-08-12 Bank Of America Corporation Service and project request processing within a business enterprise
US8924692B2 (en) 2009-12-26 2014-12-30 Intel Corporation Event counter checkpointing and restoring
US20120227045A1 (en) * 2009-12-26 2012-09-06 Knauth Laura A Method, apparatus, and system for speculative execution event counter checkpointing and restoring
US8635566B2 (en) * 2011-12-20 2014-01-21 Advanced Micro Devices, Inc. Parity error detection verification
GB2514618B (en) * 2013-05-31 2020-11-11 Advanced Risc Mach Ltd Data processing systems
US9619230B2 (en) 2013-06-28 2017-04-11 International Business Machines Corporation Predictive fetching and decoding for selected instructions
US9513924B2 (en) * 2013-06-28 2016-12-06 Globalfoundries Inc. Predictor data structure for use in pipelined processing
US10503513B2 (en) * 2013-10-23 2019-12-10 Nvidia Corporation Dispatching a stored instruction in response to determining that a received instruction is of a same instruction type
US10372458B2 (en) * 2015-04-01 2019-08-06 Huawei Technologies Co., Ltd Method and apparatus for a self-clocked, event triggered superscalar processor
US9645637B2 (en) 2015-09-04 2017-05-09 International Business Machines Corporation Managing a free list of resources to decrease control complexity and reduce power consumption
US9977677B2 (en) 2016-04-07 2018-05-22 International Business Machines Corporation Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port
GB2572954B (en) * 2018-04-16 2020-12-30 Advanced Risc Mach Ltd An apparatus and method for prefetching data items

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1183275A (en) * 1981-10-02 1985-02-26 Martin J. Schwartz Byte addressable memory for variable length instructions and data
US4654781A (en) * 1981-10-02 1987-03-31 Raytheon Company Byte addressable memory for variable length instructions and data
US4916652A (en) * 1987-09-30 1990-04-10 International Business Machines Corporation Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures
US5247628A (en) * 1987-11-30 1993-09-21 International Business Machines Corporation Parallel processor instruction dispatch apparatus with interrupt handler
EP0363176B1 (de) * 1988-10-07 1996-02-14 International Business Machines Corporation Prozessoren für wortorganisierte Daten
US5127093A (en) * 1989-01-17 1992-06-30 Cray Research Inc. Computer look-ahead instruction issue control
US5295249A (en) * 1990-05-04 1994-03-15 International Business Machines Corporation Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
JPH052484A (ja) * 1991-06-24 1993-01-08 Mitsubishi Electric Corp スーパースカラプロセツサ
US5564118A (en) * 1992-11-12 1996-10-08 Digital Equipment Corporation Past-history filtered branch prediction
US5519841A (en) * 1992-11-12 1996-05-21 Digital Equipment Corporation Multi instruction register mapper
CA2107046A1 (en) * 1993-01-08 1994-07-09 James Allan Kahle Method and system for increased instruction dispatch efficiency in superscalar processor system
US5519864A (en) * 1993-12-27 1996-05-21 Intel Corporation Method and apparatus for scheduling the dispatch of instructions from a reservation station
US5559975A (en) * 1994-06-01 1996-09-24 Advanced Micro Devices, Inc. Program counter update mechanism

Also Published As

Publication number Publication date
EP0829045B1 (de) 2002-09-04
EP0829045A1 (de) 1998-03-18
WO1996038783A1 (en) 1996-12-05
JP3597540B2 (ja) 2004-12-08
DE69623461T2 (de) 2003-07-24
US5838940A (en) 1998-11-17
JP2001500641A (ja) 2001-01-16

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