DE69623284D1 - Datenverarbeitungsgerät und -verfahren - Google Patents

Datenverarbeitungsgerät und -verfahren

Info

Publication number
DE69623284D1
DE69623284D1 DE69623284T DE69623284T DE69623284D1 DE 69623284 D1 DE69623284 D1 DE 69623284D1 DE 69623284 T DE69623284 T DE 69623284T DE 69623284 T DE69623284 T DE 69623284T DE 69623284 D1 DE69623284 D1 DE 69623284D1
Authority
DE
Germany
Prior art keywords
data processing
processing equipment
equipment
data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69623284T
Other languages
English (en)
Other versions
DE69623284T2 (de
Inventor
Christopher Huw Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69623284D1 publication Critical patent/DE69623284D1/de
Publication of DE69623284T2 publication Critical patent/DE69623284T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1488—Digital recording or reproducing using self-clocking codes characterised by the use of three levels
    • G11B20/1492—Digital recording or reproducing using self-clocking codes characterised by the use of three levels two levels are symmetric, in respect of the sign to the third level which is "zero"
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/146—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by using digital means for generating the oscillator control signal
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means
DE69623284T 1996-09-24 1996-09-24 Datenverarbeitungsgerät und -verfahren Expired - Lifetime DE69623284T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96306940A EP0831483B1 (de) 1996-09-24 1996-09-24 Datenverarbeitungsgerät und -verfahren

Publications (2)

Publication Number Publication Date
DE69623284D1 true DE69623284D1 (de) 2002-10-02
DE69623284T2 DE69623284T2 (de) 2003-04-17

Family

ID=8225095

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69623284T Expired - Lifetime DE69623284T2 (de) 1996-09-24 1996-09-24 Datenverarbeitungsgerät und -verfahren

Country Status (4)

Country Link
US (1) US5896067A (de)
EP (1) EP0831483B1 (de)
JP (1) JP3967800B2 (de)
DE (1) DE69623284T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69617677T2 (de) * 1996-09-24 2002-08-08 Hewlett Packard Co Datenverarbeitungsgerät und -verfahren
JPH11154377A (ja) * 1997-09-17 1999-06-08 Sony Corp データ記録装置及び方法、並びにデータ再生装置及び方法
US6771725B2 (en) * 1998-11-09 2004-08-03 Broadcom Corporation Multi-pair gigabit ethernet transceiver
US6477200B1 (en) * 1998-11-09 2002-11-05 Broadcom Corporation Multi-pair gigabit ethernet transceiver
KR20000042571A (ko) * 1998-12-26 2000-07-15 전주범 디지탈 브이씨알의 재생 등화기
JP3767238B2 (ja) * 1999-03-26 2006-04-19 松下電器産業株式会社 信号処理装置
US6484286B1 (en) * 1999-09-01 2002-11-19 Lsi Logic Corporation Error signal calculation from a Viterbi output
US7333570B2 (en) 2000-03-14 2008-02-19 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
WO2002005428A2 (en) * 2000-07-10 2002-01-17 Silicon Laboratories, Inc. Digitally-synthesized loop filter circuit particularly useful for a phase locked loop
US6701140B1 (en) * 2000-09-14 2004-03-02 3Com Corporation Digital receive phase lock loop with cumulative phase error correction and dynamically programmable correction rate
GB2377349B (en) * 2001-07-07 2004-10-13 Hewlett Packard Co Adaptive filter control
JP3808343B2 (ja) * 2001-10-03 2006-08-09 三菱電機株式会社 Ｐｌｌ回路
US6549079B1 (en) 2001-11-09 2003-04-15 Analog Devices, Inc. Feedback systems for enhanced oscillator switching time
GB2383697A (en) * 2001-12-27 2003-07-02 Zarlink Semiconductor Inc Method of speeding lock of PLL
US8306176B2 (en) * 2002-06-19 2012-11-06 Texas Instruments Incorporated Fine-grained gear-shifting of a digital phase-locked loop (PLL)
US7839178B2 (en) * 2002-08-20 2010-11-23 Seagate Technology Llc High speed digital phase/frequency comparator for phase locked loops
US7092472B2 (en) * 2003-09-16 2006-08-15 Rambus Inc. Data-level clock recovery
US7397848B2 (en) * 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7126378B2 (en) * 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US7233164B2 (en) * 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system
US7738617B1 (en) 2004-09-29 2010-06-15 Pmc-Sierra, Inc. Clock and data recovery locking technique for large frequency offsets
US11153129B1 (en) * 2020-06-01 2021-10-19 International Business Machines Corporation Feedforward equalizer with programmable roaming taps
CN117249846B (zh) * 2023-11-17 2024-02-09 浙江明哲电子科技有限公司 一种编码器预解码处理方法、系统及存储介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231071A (en) * 1978-07-17 1980-10-28 Digital Equipment Corporation Reader for data recorded on magnetic disks at plural densities
US4590602A (en) * 1983-08-18 1986-05-20 General Signal Wide range clock recovery circuit
US4672637A (en) * 1985-07-31 1987-06-09 Halpern Peter H Adaptive bit synchronizer
US4847876A (en) * 1986-12-31 1989-07-11 Raytheon Company Timing recovery scheme for burst communication systems
US4872155A (en) * 1987-03-13 1989-10-03 Pioneer Electronic Corporation Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock
US4896336A (en) * 1988-08-29 1990-01-23 Rockwell International Corporation Differential phase-shift keying demodulator
US5065413A (en) * 1989-12-09 1991-11-12 Sony Corporation Phase locked loop circuit
US5015970A (en) * 1990-02-15 1991-05-14 Advanced Micro Devices, Inc. Clock recovery phase lock loop having digitally range limited operating window
US5159292A (en) * 1992-02-25 1992-10-27 Thomson Consumer Electronics, Inc. Adaptive phase locked loop
GB9324918D0 (en) * 1993-12-04 1994-01-26 Hewlett Packard Ltd High-density data recording
US5512860A (en) * 1994-12-02 1996-04-30 Pmc-Sierra, Inc. Clock recovery phase locked loop control using clock difference detection and forced low frequency startup

Also Published As

Publication number Publication date
EP0831483A1 (de) 1998-03-25
DE69623284T2 (de) 2003-04-17
JP3967800B2 (ja) 2007-08-29
US5896067A (en) 1999-04-20
JPH10134523A (ja) 1998-05-22
EP0831483B1 (de) 2002-08-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE