DE69622301D1 - Konsistenzprüfung einer Instruktionsverarbeitungsfolge für ein Multiprozessorsystem - Google Patents

Konsistenzprüfung einer Instruktionsverarbeitungsfolge für ein Multiprozessorsystem

Info

Publication number
DE69622301D1
DE69622301D1 DE69622301T DE69622301T DE69622301D1 DE 69622301 D1 DE69622301 D1 DE 69622301D1 DE 69622301 T DE69622301 T DE 69622301T DE 69622301 T DE69622301 T DE 69622301T DE 69622301 D1 DE69622301 D1 DE 69622301D1
Authority
DE
Germany
Prior art keywords
processing sequence
multiprocessor system
instruction processing
consistency check
consistency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69622301T
Other languages
English (en)
Other versions
DE69622301T2 (de
Inventor
Nadeem Malik
Brian O'krafka
Avijit Saha
Shahram Salamian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69622301D1 publication Critical patent/DE69622301D1/de
Application granted granted Critical
Publication of DE69622301T2 publication Critical patent/DE69622301T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
DE69622301T 1995-03-16 1996-02-21 Konsistenzprüfung einer Instruktionsverarbeitungsfolge für ein Multiprozessorsystem Expired - Fee Related DE69622301T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/405,058 US5692153A (en) 1995-03-16 1995-03-16 Method and system for verifying execution order within a multiprocessor data processing system

Publications (2)

Publication Number Publication Date
DE69622301D1 true DE69622301D1 (de) 2002-08-22
DE69622301T2 DE69622301T2 (de) 2003-02-20

Family

ID=23602115

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69622301T Expired - Fee Related DE69622301T2 (de) 1995-03-16 1996-02-21 Konsistenzprüfung einer Instruktionsverarbeitungsfolge für ein Multiprozessorsystem

Country Status (4)

Country Link
US (1) US5692153A (de)
EP (1) EP0732652B1 (de)
JP (1) JP3382080B2 (de)
DE (1) DE69622301T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5893152A (en) * 1996-03-08 1999-04-06 Sun Microsystems, Inc. Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory
US6021261A (en) * 1996-12-05 2000-02-01 International Business Machines Corporation Method and system for testing a multiprocessor data processing system utilizing a plurality of event tracers
US6240490B1 (en) 1998-07-20 2001-05-29 International Business Machines Corporation Comprehensive multilevel cache preloading mechanism in a multiprocessing simulation environment
US6681320B1 (en) * 1999-12-29 2004-01-20 Intel Corporation Causality-based memory ordering in a multiprocessing environment
US8055492B2 (en) * 2002-01-10 2011-11-08 International Business Machines Corporation Non-unique results in design verification by test programs
US7496494B2 (en) 2002-09-17 2009-02-24 International Business Machines Corporation Method and system for multiprocessor emulation on a multiprocessor host system
US7953588B2 (en) 2002-09-17 2011-05-31 International Business Machines Corporation Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host
US9043194B2 (en) * 2002-09-17 2015-05-26 International Business Machines Corporation Method and system for efficient emulation of multiprocessor memory consistency
US7146607B2 (en) 2002-09-17 2006-12-05 International Business Machines Corporation Method and system for transparent dynamic optimization in a multiprocessing environment
US8108843B2 (en) 2002-09-17 2012-01-31 International Business Machines Corporation Hybrid mechanism for more efficient emulation and method therefor
US6892286B2 (en) * 2002-09-30 2005-05-10 Sun Microsystems, Inc. Shared memory multiprocessor memory model verification system and method
US7779393B1 (en) * 2005-05-25 2010-08-17 Oracle America, Inc. System and method for efficient verification of memory consistency model compliance
GB0623276D0 (en) * 2006-11-22 2007-01-03 Transitive Ltd Memory consistency protection in a multiprocessor computing system
US7814378B2 (en) * 2007-05-18 2010-10-12 Oracle America, Inc. Verification of memory consistency and transactional memory
US20190370038A1 (en) * 2016-07-27 2019-12-05 Intel Corporation Apparatus and method supporting code optimization

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5148533A (en) * 1989-01-05 1992-09-15 Bull Hn Information Systems Inc. Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units
US5247648A (en) * 1990-04-12 1993-09-21 Sun Microsystems, Inc. Maintaining data coherency between a central cache, an I/O cache and a memory
US5347648A (en) * 1990-06-29 1994-09-13 Digital Equipment Corporation Ensuring write ordering under writeback cache error conditions
US5276852A (en) * 1990-10-01 1994-01-04 Digital Equipment Corporation Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions
JP2743608B2 (ja) * 1991-03-27 1998-04-22 日本電気株式会社 共有レジスタ制御方式
US5265232A (en) * 1991-04-03 1993-11-23 International Business Machines Corporation Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data
US5265233A (en) * 1991-05-17 1993-11-23 Sun Microsystems, Inc. Method and apparatus for providing total and partial store ordering for a memory in multi-processor system
US5301298A (en) * 1991-10-11 1994-04-05 Intel Corporation Processor for multiple cache coherent protocols
US5379396A (en) * 1991-10-11 1995-01-03 Intel Corporation Write ordering for microprocessor depending on cache hit and write buffer content
US5398325A (en) * 1992-05-07 1995-03-14 Sun Microsystems, Inc. Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems

Also Published As

Publication number Publication date
EP0732652A1 (de) 1996-09-18
JPH08272686A (ja) 1996-10-18
JP3382080B2 (ja) 2003-03-04
EP0732652B1 (de) 2002-07-17
US5692153A (en) 1997-11-25
DE69622301T2 (de) 2003-02-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee