DE69621114T2 - Verfahren zum Steuern des Schreibens von Daten in einen auf einer Karte befindlichen Mikrocomputer - Google Patents

Verfahren zum Steuern des Schreibens von Daten in einen auf einer Karte befindlichen Mikrocomputer

Info

Publication number
DE69621114T2
DE69621114T2 DE69621114T DE69621114T DE69621114T2 DE 69621114 T2 DE69621114 T2 DE 69621114T2 DE 69621114 T DE69621114 T DE 69621114T DE 69621114 T DE69621114 T DE 69621114T DE 69621114 T2 DE69621114 T2 DE 69621114T2
Authority
DE
Germany
Prior art keywords
microcomputer
writing
card
controlling
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69621114T
Other languages
English (en)
Other versions
DE69621114D1 (de
Inventor
Hiroshi Hikichi
Takashi Igaue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69621114D1 publication Critical patent/DE69621114D1/de
Application granted granted Critical
Publication of DE69621114T2 publication Critical patent/DE69621114T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Microcomputers (AREA)
  • Read Only Memory (AREA)
DE69621114T 1996-01-17 1996-12-27 Verfahren zum Steuern des Schreibens von Daten in einen auf einer Karte befindlichen Mikrocomputer Expired - Fee Related DE69621114T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP589096A JP3076239B2 (ja) 1996-01-17 1996-01-17 オンボード書込制御方法

Publications (2)

Publication Number Publication Date
DE69621114D1 DE69621114D1 (de) 2002-06-13
DE69621114T2 true DE69621114T2 (de) 2002-11-07

Family

ID=11623498

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69621114T Expired - Fee Related DE69621114T2 (de) 1996-01-17 1996-12-27 Verfahren zum Steuern des Schreibens von Daten in einen auf einer Karte befindlichen Mikrocomputer

Country Status (5)

Country Link
US (1) US5835706A (de)
EP (1) EP0785508B1 (de)
JP (1) JP3076239B2 (de)
KR (1) KR100242518B1 (de)
DE (1) DE69621114T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1063581A (ja) * 1996-08-26 1998-03-06 Nec Corp メモリ書き込み制御回路
US6144887A (en) 1996-12-09 2000-11-07 Denso Corporation Electronic control unit with reset blocking during loading
JP3314749B2 (ja) * 1999-02-17 2002-08-12 株式会社デンソー 電子制御装置
US6389500B1 (en) * 1999-05-28 2002-05-14 Agere Systems Guardian Corporation Flash memory
DE10052877B4 (de) * 1999-10-21 2008-07-03 Samsung Electronics Co., Ltd., Suwon Mikrocontroller
US6928362B2 (en) * 2003-06-06 2005-08-09 John Meaney System and method for real time programmability of an engine control unit
US6973299B2 (en) * 2003-08-01 2005-12-06 Microsoft Corporation Unified contact list

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349669A (en) * 1988-12-21 1994-09-20 Oki Electric Industry Co., Ltd. Data write control means
JPH04109547A (ja) * 1990-08-30 1992-04-10 Sharp Corp メモリデータ保護装置
JPH04160539A (ja) * 1990-10-24 1992-06-03 Mitsubishi Electric Corp マイクロコンピュータ
JPH0729386A (ja) * 1993-07-13 1995-01-31 Hitachi Ltd フラッシュメモリ及びマイクロコンピュータ
DE4332769C1 (de) * 1993-09-25 1994-12-15 Bosch Gmbh Robert Mikrorechner
JPH07271634A (ja) * 1994-03-29 1995-10-20 Hitachi Ltd フラッシュｅｅｐｒｏｍを備えた制御装置

Also Published As

Publication number Publication date
KR970059933A (ko) 1997-08-12
EP0785508A3 (de) 1997-12-10
DE69621114D1 (de) 2002-06-13
EP0785508A2 (de) 1997-07-23
JPH09198320A (ja) 1997-07-31
US5835706A (en) 1998-11-10
JP3076239B2 (ja) 2000-08-14
KR100242518B1 (ko) 2000-02-01
EP0785508B1 (de) 2002-05-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee