DE69619373D1 - Verfahren und gerät um fehlercodes wirksam zu speichern - Google Patents

Verfahren und gerät um fehlercodes wirksam zu speichern

Info

Publication number
DE69619373D1
DE69619373D1 DE69619373T DE69619373T DE69619373D1 DE 69619373 D1 DE69619373 D1 DE 69619373D1 DE 69619373 T DE69619373 T DE 69619373T DE 69619373 T DE69619373 T DE 69619373T DE 69619373 D1 DE69619373 D1 DE 69619373D1
Authority
DE
Germany
Prior art keywords
error codes
storing error
effectively storing
effectively
codes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69619373T
Other languages
English (en)
Other versions
DE69619373T2 (de
Inventor
Nirmal Saxena
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69619373D1 publication Critical patent/DE69619373D1/de
Application granted granted Critical
Publication of DE69619373T2 publication Critical patent/DE69619373T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69619373T 1995-06-23 1996-06-10 Verfahren und gerät um fehlercodes wirksam zu speichern Expired - Lifetime DE69619373T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/494,150 US5734664A (en) 1995-06-23 1995-06-23 Method and apparatus to efficiently store error codes
PCT/US1996/009682 WO1997001138A1 (en) 1995-06-23 1996-06-10 Method and apparatus to efficiently store error codes

Publications (2)

Publication Number Publication Date
DE69619373D1 true DE69619373D1 (de) 2002-03-28
DE69619373T2 DE69619373T2 (de) 2002-07-11

Family

ID=23963248

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69619373T Expired - Lifetime DE69619373T2 (de) 1995-06-23 1996-06-10 Verfahren und gerät um fehlercodes wirksam zu speichern

Country Status (5)

Country Link
US (1) US5734664A (de)
EP (1) EP0834126B1 (de)
JP (1) JP3869006B2 (de)
DE (1) DE69619373T2 (de)
WO (1) WO1997001138A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3184129B2 (ja) 1997-09-29 2001-07-09 甲府日本電気株式会社 記憶装置
US6662333B1 (en) * 2000-02-04 2003-12-09 Hewlett-Packard Development Company, L.P. Shared error correction for memory design
US6751769B2 (en) 2000-06-06 2004-06-15 International Business Machines Corporation (146,130) error correction code utilizing address information
US6785837B1 (en) 2000-11-20 2004-08-31 International Business Machines Corporation Fault tolerant memory system utilizing memory arrays with hard error detection
US7237176B2 (en) * 2004-01-12 2007-06-26 Hewlett-Packard Development Company, L.P. Partitioning data for error correction
KR100746225B1 (ko) * 2006-02-13 2007-08-03 삼성전자주식회사 반도체 메모리 장치 및 이를 구비한 메모리 시스템
US7292950B1 (en) * 2006-05-08 2007-11-06 Cray Inc. Multiple error management mode memory module
US8612828B2 (en) * 2009-12-22 2013-12-17 Intel Corporation Error correction mechanisms for 8-bit memory devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5206855A (en) * 1990-04-06 1993-04-27 Motorola, Inc. Multiple frequency message system
US5206865A (en) * 1990-12-17 1993-04-27 Motorola, Inc. Error detection and correction memory system
JPH04290144A (ja) * 1991-03-19 1992-10-14 Hitachi Ltd メモリ拡張方式
US5490155A (en) * 1992-10-02 1996-02-06 Compaq Computer Corp. Error correction system for n bits using error correcting code designed for fewer than n bits

Also Published As

Publication number Publication date
JP2000500252A (ja) 2000-01-11
WO1997001138A1 (en) 1997-01-09
US5734664A (en) 1998-03-31
EP0834126B1 (de) 2002-02-20
EP0834126A1 (de) 1998-04-08
DE69619373T2 (de) 2002-07-11
JP3869006B2 (ja) 2007-01-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE