DE69613056T2 - Schnittstelleneinrichtung zwischen einem Rechner redundanter Architektur und einem Kommunikationsmittel - Google Patents
Schnittstelleneinrichtung zwischen einem Rechner redundanter Architektur und einem KommunikationsmittelInfo
- Publication number
- DE69613056T2 DE69613056T2 DE69613056T DE69613056T DE69613056T2 DE 69613056 T2 DE69613056 T2 DE 69613056T2 DE 69613056 T DE69613056 T DE 69613056T DE 69613056 T DE69613056 T DE 69613056T DE 69613056 T2 DE69613056 T2 DE 69613056T2
- Authority
- DE
- Germany
- Prior art keywords
- computer
- communication
- interface device
- redundant architecture
- redundant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1608—Error detection by comparing the output signals of redundant hardware
- G06F11/1625—Error detection by comparing the output signals of redundant hardware in communications, e.g. transmission, interfaces
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
- G06F11/1683—Temporal synchronisation or re-synchronisation of redundant processing components at instruction level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/83—Indexing scheme relating to error detection, to error correction, and to monitoring the solution involving signatures
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9508845A FR2737029B1 (fr) | 1995-07-19 | 1995-07-19 | Dispositif d'interface entre un calculateur a architecture redondante et un moyen de communication |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69613056D1 DE69613056D1 (de) | 2001-07-05 |
DE69613056T2 true DE69613056T2 (de) | 2002-03-21 |
Family
ID=9481222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69613056T Expired - Lifetime DE69613056T2 (de) | 1995-07-19 | 1996-06-20 | Schnittstelleneinrichtung zwischen einem Rechner redundanter Architektur und einem Kommunikationsmittel |
Country Status (4)
Country | Link |
---|---|
US (1) | US5778206A (de) |
EP (1) | EP0755010B1 (de) |
DE (1) | DE69613056T2 (de) |
FR (1) | FR2737029B1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102019106410A1 (de) * | 2019-03-13 | 2020-09-17 | Liebherr-Aerospace Lindenberg Gmbh | Vorrichtung und Verfahren zur Datenübertragung |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5953352A (en) * | 1997-06-23 | 1999-09-14 | Micron Electronics, Inc. | Method of checking data integrity for a raid 1 system |
US5930484A (en) * | 1997-09-18 | 1999-07-27 | International Business Machines Corporation | Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access |
US6018780A (en) * | 1998-05-19 | 2000-01-25 | Lucent Technologies Inc. | Method and apparatus for downloading a file to a remote unit |
DE19832060C2 (de) * | 1998-07-16 | 2000-07-06 | Siemens Ag | Doppelbare Prozessoreinrichtung |
US6327670B1 (en) * | 1999-01-22 | 2001-12-04 | Lucent Technologies Inc. | Duplex processor with an update bus and method for operating the update bus |
KR100324279B1 (ko) * | 1999-08-24 | 2002-02-25 | 서평원 | 교환기에서 이중화 프로세서 간 메모리 일치 시스템 및 방법 |
FR2803057B1 (fr) * | 1999-12-22 | 2002-11-29 | Centre Nat Etd Spatiales | Systeme informatique tolerant aux erreurs transitoires et procede de gestion dans un tel systeme |
FR2819598B1 (fr) * | 2001-01-16 | 2003-04-11 | Thomson Csf | Dispositif de synchronisation tolerant aux pannes pour reseau informatique temps reel |
US6630872B1 (en) | 2001-07-20 | 2003-10-07 | Cmc Electronics, Inc. | Digital indirectly compensated crystal oscillator |
FR2844946B1 (fr) * | 2002-03-15 | 2004-10-22 | Thales Sa | Procede de selection et de tri de paquets mis a disposition d'un equipement par un reseau de transmission de donnees par paquets |
FR2840482B1 (fr) * | 2002-05-28 | 2004-10-15 | Thales Sa | Procede de reconstitution de messages achemines par un ou plusieurs reseaux de transmission par paquets |
JP2004046455A (ja) * | 2002-07-10 | 2004-02-12 | Nec Corp | 情報処理装置 |
US6813527B2 (en) * | 2002-11-20 | 2004-11-02 | Honeywell International Inc. | High integrity control system architecture using digital computing platforms with rapid recovery |
US7484148B2 (en) * | 2002-12-11 | 2009-01-27 | Analog Devices, Inc. | Interface error monitor system and method |
US20040154017A1 (en) * | 2003-01-31 | 2004-08-05 | International Business Machines Corporation | A Method and Apparatus For Dynamically Allocating Process Resources |
DE10340236B4 (de) * | 2003-08-29 | 2006-06-01 | Infineon Technologies Ag | Anordnung mit einer Datenverarbeitungseinrichtung und einem Speicher |
JP2006178636A (ja) * | 2004-12-21 | 2006-07-06 | Nec Corp | フォールトトレラントコンピュータ、およびその制御方法 |
JP2006293929A (ja) * | 2005-04-14 | 2006-10-26 | Matsushita Electric Ind Co Ltd | データ伝送装置 |
US7516246B2 (en) * | 2005-10-27 | 2009-04-07 | International Business Machines Corporation | Communications channel method for verifying integrity of untrusted subsystem responses to a request |
FR2901379B1 (fr) | 2006-05-19 | 2008-06-27 | Airbus France Sas | Procede et dispositif de consolidation par synchronisation logicielle dans les calculateurs des commandes de vol |
US8898536B2 (en) * | 2007-04-27 | 2014-11-25 | Netapp, Inc. | Multi-core engine for detecting bit errors |
FR2925191B1 (fr) * | 2007-12-14 | 2010-03-05 | Thales Sa | Architecture de traitement numerique a haute integrite a multiples ressources supervisees |
US9158579B1 (en) | 2008-11-10 | 2015-10-13 | Netapp, Inc. | System having operation queues corresponding to operation execution time |
US10057365B1 (en) * | 2015-06-24 | 2018-08-21 | Amazon Technologies, Inc. | Asynchronous provision of resource status data |
US11842224B1 (en) | 2017-09-01 | 2023-12-12 | Amazon Technologies, Inc. | Synchronous and asynchronous responses to data requests from remote devices |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1179069A (en) * | 1981-04-10 | 1984-12-04 | Yasushi Fukunaga | Data transmission apparatus for a multiprocessor system |
US4543627A (en) * | 1981-12-14 | 1985-09-24 | At&T Bell Laboratories | Internal communication arrangement for a multiprocessor system |
DE3328405A1 (de) * | 1983-08-05 | 1985-02-21 | Siemens AG, 1000 Berlin und 8000 München | Steuerorgane eines fehlertoleranten mehrrechnersystems |
US4625307A (en) * | 1984-12-13 | 1986-11-25 | United Technologies Corporation | Apparatus for interfacing between at least one channel and at least one bus |
EP0408810B1 (de) * | 1989-07-20 | 1996-03-20 | Kabushiki Kaisha Toshiba | Mehrprozessor-Computersystem |
US5226152A (en) * | 1990-12-07 | 1993-07-06 | Motorola, Inc. | Functional lockstep arrangement for redundant processors |
DE69332853T2 (de) * | 1992-09-07 | 2004-03-11 | Hitachi, Ltd. | Multiprozessorsystem und Kommunikationsverfahren zwischen Prozessoren |
US5491787A (en) * | 1994-08-25 | 1996-02-13 | Unisys Corporation | Fault tolerant digital computer system having two processors which periodically alternate as master and slave |
-
1995
- 1995-07-19 FR FR9508845A patent/FR2737029B1/fr not_active Expired - Lifetime
-
1996
- 1996-06-20 DE DE69613056T patent/DE69613056T2/de not_active Expired - Lifetime
- 1996-06-20 EP EP96401354A patent/EP0755010B1/de not_active Expired - Lifetime
- 1996-07-19 US US08/690,156 patent/US5778206A/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102019106410A1 (de) * | 2019-03-13 | 2020-09-17 | Liebherr-Aerospace Lindenberg Gmbh | Vorrichtung und Verfahren zur Datenübertragung |
CN111698016A (zh) * | 2019-03-13 | 2020-09-22 | 利勃海尔航空航天林登贝格股份有限公司 | 用于数据传输的设备和方法 |
CN111698016B (zh) * | 2019-03-13 | 2024-04-26 | 利勃海尔航空航天林登贝格股份有限公司 | 用于数据传输的设备和方法 |
Also Published As
Publication number | Publication date |
---|---|
EP0755010B1 (de) | 2001-05-30 |
US5778206A (en) | 1998-07-07 |
FR2737029A1 (fr) | 1997-01-24 |
DE69613056D1 (de) | 2001-07-05 |
FR2737029B1 (fr) | 1997-09-26 |
EP0755010A1 (de) | 1997-01-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |