DE69612007D1 - Ausgangspuffer mit gemeinsam genutzten zwischenknoten - Google Patents

Ausgangspuffer mit gemeinsam genutzten zwischenknoten

Info

Publication number
DE69612007D1
DE69612007D1 DE69612007T DE69612007T DE69612007D1 DE 69612007 D1 DE69612007 D1 DE 69612007D1 DE 69612007 T DE69612007 T DE 69612007T DE 69612007 T DE69612007 T DE 69612007T DE 69612007 D1 DE69612007 D1 DE 69612007D1
Authority
DE
Germany
Prior art keywords
intermediate nodes
initial buffer
shared intermediate
shared
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69612007T
Other languages
English (en)
Other versions
DE69612007T2 (de
Inventor
J Lotfi
D Porter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lattice Semiconductor Corp
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69612007D1 publication Critical patent/DE69612007D1/de
Application granted granted Critical
Publication of DE69612007T2 publication Critical patent/DE69612007T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE69612007T 1995-09-01 1996-07-11 Ausgangspuffer mit gemeinsam genutzten zwischenknoten Expired - Fee Related DE69612007T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52306895A 1995-09-01 1995-09-01
PCT/US1996/011554 WO1997009784A1 (en) 1995-09-01 1996-07-11 Output buffer incorporating shared intermediate nodes

Publications (2)

Publication Number Publication Date
DE69612007D1 true DE69612007D1 (de) 2001-04-12
DE69612007T2 DE69612007T2 (de) 2001-10-25

Family

ID=24083531

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69612007T Expired - Fee Related DE69612007T2 (de) 1995-09-01 1996-07-11 Ausgangspuffer mit gemeinsam genutzten zwischenknoten

Country Status (6)

Country Link
US (1) US5717342A (de)
EP (1) EP0847623B1 (de)
JP (1) JPH11512572A (de)
KR (1) KR19990044240A (de)
DE (1) DE69612007T2 (de)
WO (1) WO1997009784A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2171052C (en) * 1995-09-29 2001-05-15 Colin Harris A tristatable output driver for use with 3.3 or 5 volt cmos logic
US5917358A (en) * 1997-12-09 1999-06-29 Motorola, Inc. Method and output buffer with programmable bias to accommodate multiple supply voltages
US6236237B1 (en) * 1998-02-27 2001-05-22 Altera Corporation Output buffer predriver with edge compensation
US6181166B1 (en) * 1998-06-19 2001-01-30 Intel Corporation Tristate driver for integrated circuit interconnects
DE10136320B4 (de) * 2001-07-26 2008-05-15 Infineon Technologies Ag Anordnung und Verfahren zum Umschalten von Transistoren
US6996640B1 (en) 2001-08-07 2006-02-07 Adaptec, Inc. Method and system for asynchronously transferring data
US6664805B2 (en) 2002-01-30 2003-12-16 Agilent Technologies, Inc. Switched capacitor piecewise linear slew rate control methods for output devices
KR100498453B1 (ko) * 2002-11-04 2005-07-01 삼성전자주식회사 출력 데이터의 스큐를 감소시킬 수 있는 출력버퍼 회로
KR100928750B1 (ko) 2003-08-07 2009-11-25 매그나칩 반도체 유한회사 버퍼 장치 및 그의 구동 방법
US7005886B2 (en) * 2004-04-30 2006-02-28 Agilent Technologies, Inc. Tristateable CMOS driver with controlled slew rate for integrated circuit I/O pads
US7088129B2 (en) * 2004-04-30 2006-08-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers
DE102004049194B3 (de) * 2004-10-08 2006-02-02 Infineon Technologies Ag Vorstufe für einen externen Treiber (OCD)
US20070024317A1 (en) * 2005-07-29 2007-02-01 Hansen James E Apparatus for obtaining precision integrated resistors
JP2007188395A (ja) * 2006-01-16 2007-07-26 Elpida Memory Inc クロック信号発生回路
US7471121B2 (en) * 2006-12-21 2008-12-30 System General Corp. Transistor drive circuit of power converter operating in a wide voltage range
JP2011018438A (ja) * 2010-09-13 2011-01-27 Renesas Electronics Corp 半導体装置
CN102684458A (zh) * 2012-05-09 2012-09-19 矽力杰半导体技术(杭州)有限公司 一种功率开关管的驱动电路以及应用其的开关电源电路
KR102555212B1 (ko) 2017-12-29 2023-07-12 엘지디스플레이 주식회사 발광 표시 장치

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59133624A (ja) * 1983-01-20 1984-08-01 Sharp Corp インタ−フエイス方式
US4743781A (en) * 1986-07-03 1988-05-10 International Business Machines Corporation Dotting circuit with inhibit function
US5066873A (en) * 1989-12-04 1991-11-19 Altera Corporation Integrated circuits with reduced switching noise
US5111074A (en) * 1990-07-26 1992-05-05 Regents Of The University Of Minnesota Multi-input compound function complementary noise-immune logic
US5111064A (en) * 1990-09-05 1992-05-05 Vlsi Technology, Inc. Slow ramp high drive output pad
JPH04146650A (ja) * 1990-10-08 1992-05-20 Mitsubishi Electric Corp 半導体集積回路装置
US5221865A (en) * 1991-06-21 1993-06-22 Crosspoint Solutions, Inc. Programmable input/output buffer circuit with test capability
US5583457A (en) * 1992-04-14 1996-12-10 Hitachi, Ltd. Semiconductor integrated circuit device having power reduction mechanism
JPH05335927A (ja) * 1992-06-02 1993-12-17 Toshiba Corp 半導体装置
US5319252A (en) * 1992-11-05 1994-06-07 Xilinx, Inc. Load programmable output buffer
US5479123A (en) * 1993-06-18 1995-12-26 Digital Equipment Corporation Externally programmable integrated bus terminator for optimizing system bus performance
JP3507534B2 (ja) * 1993-10-20 2004-03-15 株式会社東芝 半導体装置
EP0690510B1 (de) * 1994-06-28 1998-05-06 Nippon Telegraph And Telephone Corporation SOI (Silizium auf Isolator)-Logikschaltung mit niedriger Spannung
US5604454A (en) * 1995-09-29 1997-02-18 Motorola Inc. Integrated circuit with low output buffer energy consumption and related method

Also Published As

Publication number Publication date
JPH11512572A (ja) 1999-10-26
US5717342A (en) 1998-02-10
EP0847623B1 (de) 2001-03-07
EP0847623A1 (de) 1998-06-17
KR19990044240A (ko) 1999-06-25
DE69612007T2 (de) 2001-10-25
WO1997009784A1 (en) 1997-03-13

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: VANTIS CORPORATION, SUNNYVALE, CALIF., US

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: LATTICE SEMICONDUCTOR CORP., (N.D.GES.D. STAATES D

8339 Ceased/non-payment of the annual fee