DE69609847D1 - Verfahren ung gerät zur erkennung von mehreren signalen - Google Patents

Verfahren ung gerät zur erkennung von mehreren signalen

Info

Publication number
DE69609847D1
DE69609847D1 DE69609847T DE69609847T DE69609847D1 DE 69609847 D1 DE69609847 D1 DE 69609847D1 DE 69609847 T DE69609847 T DE 69609847T DE 69609847 T DE69609847 T DE 69609847T DE 69609847 D1 DE69609847 D1 DE 69609847D1
Authority
DE
Germany
Prior art keywords
multiple signals
detecting multiple
detecting
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69609847T
Other languages
English (en)
Other versions
DE69609847T2 (de
Inventor
W Priebe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Application granted granted Critical
Publication of DE69609847D1 publication Critical patent/DE69609847D1/de
Publication of DE69609847T2 publication Critical patent/DE69609847T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices

Landscapes

  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Dram (AREA)
DE69609847T 1995-09-13 1996-09-11 Verfahren ung gerät zur erkennung von mehreren signalen Expired - Lifetime DE69609847T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/527,660 US5610573A (en) 1995-09-13 1995-09-13 Method and apparatus for detecting assertion of multiple signals
PCT/US1996/014813 WO1997010603A1 (en) 1995-09-13 1996-09-11 Method and apparatus for detecting assertion of multiple signals

Publications (2)

Publication Number Publication Date
DE69609847D1 true DE69609847D1 (de) 2000-09-21
DE69609847T2 DE69609847T2 (de) 2001-03-29

Family

ID=24102396

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69609847T Expired - Lifetime DE69609847T2 (de) 1995-09-13 1996-09-11 Verfahren ung gerät zur erkennung von mehreren signalen

Country Status (5)

Country Link
US (2) US5610573A (de)
EP (1) EP0850482B1 (de)
JP (1) JPH11512550A (de)
DE (1) DE69609847T2 (de)
WO (1) WO1997010603A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610573A (en) * 1995-09-13 1997-03-11 Lsi Logic Corporation Method and apparatus for detecting assertion of multiple signals
CA2273665A1 (en) 1999-06-07 2000-12-07 Mosaid Technologies Incorporated Differential sensing amplifier for content addressable memory
CA2277717C (en) * 1999-07-12 2006-12-05 Mosaid Technologies Incorporated Circuit and method for multiple match detection in content addressable memories
US6622267B1 (en) * 1999-12-08 2003-09-16 Intel Corporation Method and apparatus for detecting multi-hit errors in cache
US6930516B2 (en) * 2001-05-30 2005-08-16 Agere Systems Inc. Comparator circuits having non-complementary input structures
US6717876B2 (en) 2001-12-28 2004-04-06 Mosaid Technologies Incorporated Matchline sensing for content addressable memories
US6618281B1 (en) * 2002-05-15 2003-09-09 International Business Machines Corporation Content addressable memory (CAM) with error checking and correction (ECC) capability
US6583656B1 (en) 2002-08-21 2003-06-24 Pericom Semiconductor Corp. Differential clock driver with transmission-gate feedback to reduce voltage-crossing sensitivity to input skew
US6924994B1 (en) 2003-03-10 2005-08-02 Integrated Device Technology, Inc. Content addressable memory (CAM) devices having scalable multiple match detection circuits therein
US7822916B1 (en) 2006-10-31 2010-10-26 Netlogic Microsystems, Inc. Integrated circuit search engine devices having priority sequencer circuits therein that sequentially encode multiple match signals
CA2868909A1 (en) * 2007-03-26 2008-10-02 Tyco Healthcare Group Lp Endoscopic surgical clip applier
US8255623B2 (en) * 2007-09-24 2012-08-28 Nvidia Corporation Ordered storage structure providing enhanced access to stored items
WO2014057546A1 (ja) * 2012-10-10 2014-04-17 富士通株式会社 マルチヒット検出回路、処理装置およびマルチヒット検出方法
US9264021B1 (en) 2014-08-29 2016-02-16 Freescale Semiconductor, Inc. Multi-bit flip-flop with enhanced fault detection
TWI670944B (zh) * 2017-08-28 2019-09-01 瑞昱半導體股份有限公司 通訊裝置及通訊方法
US10734985B2 (en) * 2018-12-17 2020-08-04 Qualcomm Incorporated Comparators for power and high-speed applications

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1310717A (fr) * 1961-10-20 1962-11-30 Electronique & Radio Ind Perfectionnements aux opérateurs logiques
US3275849A (en) * 1963-11-08 1966-09-27 Gen Electric Bistable device employing threshold gate circuits
US4040016A (en) * 1976-03-31 1977-08-02 International Business Machines Corporation Twin nodes capacitance memory
DE3227121A1 (de) * 1982-07-20 1984-01-26 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum lesen bipolarer speicherzellen
JPS6063786A (ja) * 1983-09-17 1985-04-12 Fujitsu Ltd センスアンプ
JPS60134627A (ja) * 1983-12-23 1985-07-17 Nec Corp 一致検出回路
DE3680064D1 (de) * 1985-10-09 1991-08-08 Nec Corp Differenzverstaerker-schaltungsanordnung.
JPH01248397A (ja) * 1988-03-29 1989-10-03 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US4896059A (en) * 1988-07-26 1990-01-23 Microelectronics Center Of North Carolina Circuit to perform variable threshold logic
US4964083A (en) * 1989-04-27 1990-10-16 Motorola, Inc. Non-address transition detection memory with improved access time
US4991141A (en) * 1990-02-08 1991-02-05 Texas Instruments Incorporated Sense amplifier and method for sensing the outputs of static random access memory cells
GB9007789D0 (en) * 1990-04-06 1990-06-06 Foss Richard C Method for dram sensing current control
JP2785540B2 (ja) * 1991-09-30 1998-08-13 松下電器産業株式会社 半導体メモリの読み出し回路
US5345419A (en) * 1993-02-10 1994-09-06 At&T Bell Laboratories Fifo with word line match circuits for flag generation
US5446685A (en) * 1993-02-23 1995-08-29 Intergraph Corporation Pulsed ground circuit for CAM and PAL memories
US5446686A (en) * 1994-08-02 1995-08-29 Sun Microsystems, Inc. Method and appartus for detecting multiple address matches in a content addressable memory
US5610573A (en) * 1995-09-13 1997-03-11 Lsi Logic Corporation Method and apparatus for detecting assertion of multiple signals

Also Published As

Publication number Publication date
WO1997010603A1 (en) 1997-03-20
DE69609847T2 (de) 2001-03-29
EP0850482B1 (de) 2000-08-16
EP0850482A1 (de) 1998-07-01
US5610573A (en) 1997-03-11
JPH11512550A (ja) 1999-10-26
US5748070A (en) 1998-05-05

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Legal Events

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