DE69535598D1 - Vorrichtung und Verfahren zur Spannungssteuerung einer Schnittstelle - Google Patents

Vorrichtung und Verfahren zur Spannungssteuerung einer Schnittstelle

Info

Publication number
DE69535598D1
DE69535598D1 DE69535598T DE69535598T DE69535598D1 DE 69535598 D1 DE69535598 D1 DE 69535598D1 DE 69535598 T DE69535598 T DE 69535598T DE 69535598 T DE69535598 T DE 69535598T DE 69535598 D1 DE69535598 D1 DE 69535598D1
Authority
DE
Germany
Prior art keywords
interface
voltage control
voltage
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69535598T
Other languages
English (en)
Other versions
DE69535598T2 (de
Inventor
Phillip W Bullinger
Michael J Mcmanus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Application granted granted Critical
Publication of DE69535598D1 publication Critical patent/DE69535598D1/de
Publication of DE69535598T2 publication Critical patent/DE69535598T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018592—Coupling arrangements; Interface arrangements using field effect transistors only with a bidirectional operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Power Sources (AREA)
DE69535598T 1994-12-08 1995-12-06 Vorrichtung und Verfahren zur Spannungssteuerung einer Schnittstelle Expired - Lifetime DE69535598T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US352331 1994-12-08
US08/352,331 US5469082A (en) 1994-12-08 1994-12-08 Peripheral component interfacing system with bus voltage/logic supply comparison means

Publications (2)

Publication Number Publication Date
DE69535598D1 true DE69535598D1 (de) 2007-10-31
DE69535598T2 DE69535598T2 (de) 2008-06-19

Family

ID=23384700

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69535598T Expired - Lifetime DE69535598T2 (de) 1994-12-08 1995-12-06 Vorrichtung und Verfahren zur Spannungssteuerung einer Schnittstelle

Country Status (6)

Country Link
US (1) US5469082A (de)
EP (1) EP0716379B1 (de)
JP (1) JP3121252B2 (de)
KR (1) KR100216974B1 (de)
DE (1) DE69535598T2 (de)
TW (1) TW353163B (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07235952A (ja) * 1993-12-28 1995-09-05 Oki Electric Ind Co Ltd 信号伝送回路およびその回路を用いた信号伝送装置
US5675809A (en) * 1995-02-10 1997-10-07 Ncr Corporation Voltage control circuit for a dual voltage bus computer system
JPH08241240A (ja) * 1995-03-03 1996-09-17 Toshiba Corp コンピュータシステム
DE19510947C1 (de) * 1995-03-25 1996-11-28 Hella Kg Hueck & Co Schaltungsanordnung zum Betrieb in verschiedenen Betriebsspannungsbereichen
US5585744A (en) * 1995-10-13 1996-12-17 Cirrus Logic, Inc. Circuits systems and methods for reducing power loss during transfer of data across a conductive line
US5804985A (en) * 1996-04-02 1998-09-08 Motorola, Inc. Programmable output buffer and method for programming
US5887144A (en) * 1996-11-20 1999-03-23 International Business Machines Corp. Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches
US6058443A (en) * 1997-02-18 2000-05-02 Advanced Micro Devices, Inc. System for partitioning PC chipset functions into logic and port integrated circuits
US5883528A (en) * 1997-03-20 1999-03-16 Cirrus Logic, Inc. Five volt tolerant TTL/CMOS and CMOS/CMOS voltage conversion circuit
US5969554A (en) * 1997-06-09 1999-10-19 International Business Machines Corp. Multi-function pre-driver circuit with slew rate control, tri-state operation, and level-shifting
US5920183A (en) * 1997-10-24 1999-07-06 Stmicroelectronics, Inc. Voltage regulator for regulating its output voltage selectively with respect to more than one voltage
US5995440A (en) * 1998-07-23 1999-11-30 International Business Machines Corporation Off-chip driver and receiver circuits for multiple voltage level DRAMs
US6166561A (en) * 1999-02-26 2000-12-26 International Business Machines Corporation Method and apparatus for protecting off chip driver circuitry employing a split rail power supply
US6545521B2 (en) 2001-06-29 2003-04-08 International Business Machines Corporation Low skew, power sequence independent CMOS receiver device
JP2005092480A (ja) * 2003-09-17 2005-04-07 Hitachi Global Storage Technologies Netherlands Bv インターフェース回路及び電子機器
US7728635B2 (en) * 2005-10-28 2010-06-01 Atmel Corporation High voltage tolerant port driver
US7336109B2 (en) * 2005-10-28 2008-02-26 Atmel Corporation High voltage tolerant port driver
US20090132404A1 (en) * 2007-11-21 2009-05-21 Marie King Apportioning fraud liability
CN102193890B (zh) * 2011-05-27 2013-06-26 上海华为技术有限公司 一种同步接口的时序调整方法及装置
US8723584B2 (en) 2012-05-03 2014-05-13 Conexant Systems, Inc. Low power dual voltage mode receiver
CN102882508A (zh) * 2012-08-30 2013-01-16 广州市捷众科贸有限公司 一种简易的rs485接口极性切换电路
TWI510928B (zh) * 2013-06-07 2015-12-01 Cal Comp Electronics & Comm Co 周邊裝置及其控制方法
US9461624B2 (en) * 2014-11-17 2016-10-04 Infineon Technologies Ag Output driver slew control
CN108123709B (zh) * 2016-11-30 2021-08-06 上海复旦微电子集团股份有限公司 输出电路
CN108134601B (zh) * 2016-11-30 2021-08-06 上海复旦微电子集团股份有限公司 接口电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084637A (en) * 1989-05-30 1992-01-28 International Business Machines Corp. Bidirectional level shifting interface circuit
US5144165A (en) * 1990-12-14 1992-09-01 International Business Machines Corporation CMOS off-chip driver circuits
US5260612A (en) * 1990-12-14 1993-11-09 Dallas Semiconductor Corp. Bi-level dual mode transceiver
US5300835A (en) * 1993-02-10 1994-04-05 Cirrus Logic, Inc. CMOS low power mixed voltage bidirectional I/O buffer
US5406140A (en) * 1993-06-07 1995-04-11 National Semiconductor Corporation Voltage translation and overvoltage protection
US5396128A (en) * 1993-09-13 1995-03-07 Motorola, Inc. Output circuit for interfacing integrated circuits having different power supply potentials

Also Published As

Publication number Publication date
EP0716379B1 (de) 2007-09-19
KR960027326A (ko) 1996-07-22
US5469082A (en) 1995-11-21
DE69535598T2 (de) 2008-06-19
JP3121252B2 (ja) 2000-12-25
EP0716379A3 (de) 1998-08-19
TW353163B (en) 1999-02-21
KR100216974B1 (ko) 1999-09-01
EP0716379A2 (de) 1996-06-12
JPH08237106A (ja) 1996-09-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition