DE69525949T2 - Arbitrierungseinheit mit kreisförmiger Priorität, insbesondere für Multiprozessorsysteme mit synchronen symmetrischen Prozessoren - Google Patents

Arbitrierungseinheit mit kreisförmiger Priorität, insbesondere für Multiprozessorsysteme mit synchronen symmetrischen Prozessoren

Info

Publication number
DE69525949T2
DE69525949T2 DE69525949T DE69525949T DE69525949T2 DE 69525949 T2 DE69525949 T2 DE 69525949T2 DE 69525949 T DE69525949 T DE 69525949T DE 69525949 T DE69525949 T DE 69525949T DE 69525949 T2 DE69525949 T2 DE 69525949T2
Authority
DE
Germany
Prior art keywords
multiprocessor systems
arbitration unit
circular priority
synchronous symmetrical
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69525949T
Other languages
English (en)
Other versions
DE69525949D1 (de
Inventor
Ferruccio Zulian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull Sa Les Clayes Sous Bois Fr
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Application granted granted Critical
Publication of DE69525949D1 publication Critical patent/DE69525949D1/de
Publication of DE69525949T2 publication Critical patent/DE69525949T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
DE69525949T 1995-12-29 1995-12-29 Arbitrierungseinheit mit kreisförmiger Priorität, insbesondere für Multiprozessorsysteme mit synchronen symmetrischen Prozessoren Expired - Lifetime DE69525949T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95830560A EP0782081B1 (de) 1995-12-29 1995-12-29 Arbitrierungseinheit mit kreisförmiger Priorität, insbesondere für Multiprozessorsysteme mit synchronen symmetrischen Prozessoren

Publications (2)

Publication Number Publication Date
DE69525949D1 DE69525949D1 (de) 2002-04-25
DE69525949T2 true DE69525949T2 (de) 2002-07-25

Family

ID=8222098

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69525949T Expired - Lifetime DE69525949T2 (de) 1995-12-29 1995-12-29 Arbitrierungseinheit mit kreisförmiger Priorität, insbesondere für Multiprozessorsysteme mit synchronen symmetrischen Prozessoren

Country Status (3)

Country Link
US (1) US5870560A (de)
EP (1) EP0782081B1 (de)
DE (1) DE69525949T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6678773B2 (en) * 2000-01-13 2004-01-13 Motorola, Inc. Bus protocol independent method and structure for managing transaction priority, ordering and deadlocks in a multi-processing system
US6754752B2 (en) * 2000-01-13 2004-06-22 Freescale Semiconductor, Inc. Multiple memory coherence groups in a single system and method therefor
KR100657256B1 (ko) * 2000-07-27 2006-12-14 삼성전자주식회사 중재기 및 그 중재기를 채용한 버스 시스템
US7099972B2 (en) * 2002-07-03 2006-08-29 Sun Microsystems, Inc. Preemptive round robin arbiter
JP4266619B2 (ja) * 2002-11-25 2009-05-20 株式会社ルネサステクノロジ 調停回路
JP2004199187A (ja) * 2002-12-16 2004-07-15 Matsushita Electric Ind Co Ltd Ｃｐｕ内蔵ｌｓｉ
US20050262281A1 (en) * 2004-05-21 2005-11-24 Nayak Prakash H Managing a shared resource
US7380038B2 (en) * 2005-02-04 2008-05-27 Microsoft Corporation Priority registers for biasing access to shared resources
US7395360B1 (en) * 2005-09-21 2008-07-01 Altera Corporation Programmable chip bus arbitration logic
US20110296078A1 (en) * 2010-06-01 2011-12-01 Qualcomm Incorporated Memory pool interface methods and apparatuses
US8151025B1 (en) * 2010-12-07 2012-04-03 King Fahd University Of Petroleum & Minerals Fast round robin circuit
CN107315703B (zh) * 2017-05-17 2020-08-25 天津大学 双优先级控制型公平仲裁器
FR3091766A1 (fr) * 2019-01-16 2020-07-17 Stmicroelectronics Sa Dispositif d'arbitrage

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814974A (en) * 1982-07-02 1989-03-21 American Telephone And Telegraph Company, At&T Bell Laboratories Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements
US5377332A (en) * 1989-10-02 1994-12-27 Data General Corporation Bus arbitration algorithm and apparatus
US5072363A (en) * 1989-12-22 1991-12-10 Harris Corporation Multimode resource arbiter providing round robin arbitration or a modified priority arbitration
US5280580A (en) * 1990-05-02 1994-01-18 International Business Machines Corporation System service request processing in multiprocessor environment
DE4024029C2 (de) * 1990-07-28 1994-07-28 Teldix Gmbh Entscheidungslogik zur Priorisierung und Synchronisierung zeitlich asynchroner Signale
US5202999A (en) * 1992-01-10 1993-04-13 Digital Equipment Corporation Access request prioritization and summary device
FR2709579B1 (fr) * 1993-08-31 1995-11-17 Sgs Thomson Microelectronics Codeur de niveau de priorité.
DE59310083D1 (de) * 1993-09-24 2000-09-07 Siemens Ag Verfahren zum Lastausgleich in einem Multiprozessorsystem
US5487170A (en) * 1993-12-16 1996-01-23 International Business Machines Corporation Data processing system having dynamic priority task scheduling capabilities
TW400483B (en) * 1994-03-01 2000-08-01 Intel Corp High performance symmetric arbitration protocol with support for I/O requirements
US5710549A (en) * 1994-09-30 1998-01-20 Tandem Computers Incorporated Routing arbitration for shared resources
US5623672A (en) * 1994-12-23 1997-04-22 Cirrus Logic, Inc. Arrangement and method of arbitration for a resource with shared user request signals and dynamic priority assignment
WO1996035173A1 (en) * 1995-05-03 1996-11-07 Apple Computer, Inc. Arbitration of computer resource access requests
US5640519A (en) * 1995-09-15 1997-06-17 Intel Corporation Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme

Also Published As

Publication number Publication date
EP0782081A1 (de) 1997-07-02
US5870560A (en) 1999-02-09
EP0782081B1 (de) 2002-03-20
DE69525949D1 (de) 2002-04-25

Similar Documents

Publication Publication Date Title
DE68923845D1 (de) Synchronisierte fehlertolerante Uhren für Multiprozessorsysteme.
KR930701785A (ko) 고도의 병렬 다중프로세서 시스템용 통합 소프트웨어 아키텍쳐
DE69030523T2 (de) Synchronisierung für Multiprozessorsystem
DE68925646T2 (de) Pipeline-multiprozessorsystem
DE69423056T2 (de) Arbitrierungslogik für Mehrfachbus-Rechnersystem
DE68925763D1 (de) Verbindungs- und Zugriffsarbitrierungsanordnung für Multiprozessorsystem
DE69230093T2 (de) Multiprozessorsystem
DE69625604T2 (de) Diagnosesystem insbesondere für motormanagementsysteme
DE69428396T2 (de) Bildverarbeitungssystem mit Fliessbandarbeitsprinzip für Einzelanwendungsumgebung
DE69424221D1 (de) Mehrrechnersystem
DE69525949D1 (de) Arbitrierungseinheit mit kreisförmiger Priorität, insbesondere für Multiprozessorsysteme mit synchronen symmetrischen Prozessoren
DE69805944D1 (de) Pumpsystem mit fehlerdetektion für die klinische ernährung
DE69027253T2 (de) Multiprozessor-Cachespeichersystem
IT1288076B1 (it) Multicalcolatore elettronico numerico parallelo multiprocessore a ridondanza di processori accoppiati
DE69332058D1 (de) Mehrprozessorsystem
DE19983443T1 (de) Außer-der-Reihe-Snooping für Multiprozessor-Computersysteme
DE69615327T2 (de) Logische Adressbusarchitektur für Mehrprozessorsysteme
DE3886756T2 (de) Betriebsmittelzugriff für Multiprozessorrechnersystem.
DE69031877T2 (de) Unterbrechungssteuerung für Mehrprozessorsystem
DE68917679T2 (de) Datenübertragungsnetzwerk für Multiprozessorsysteme.
DE69622301T2 (de) Konsistenzprüfung einer Instruktionsverarbeitungsfolge für ein Multiprozessorsystem
EP0669584A3 (de) Massivparallelmehrprozessorsystem mit fehlertolerantem Zwischenprozessornetzwerk.
DE69621263D1 (de) Verteilter Datencachespeicher für Multiprozessorsystem mit Cachespeicher
DE60038761D1 (de) Rechnersystem mit mehreren parallel angeordneten Prozessoren
DE68916413D1 (de) Vermittlungssystem für den gleichzeitigen Datentransfer zwischen Datenprozessoren.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL S.A., LES CLAYES SOUS BOIS, FR