DE69523354D1 - Multiplexer - Google Patents

Multiplexer

Info

Publication number
DE69523354D1
DE69523354D1 DE69523354T DE69523354T DE69523354D1 DE 69523354 D1 DE69523354 D1 DE 69523354D1 DE 69523354 T DE69523354 T DE 69523354T DE 69523354 T DE69523354 T DE 69523354T DE 69523354 D1 DE69523354 D1 DE 69523354D1
Authority
DE
Germany
Prior art keywords
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69523354T
Other languages
English (en)
Other versions
DE69523354T2 (de
Inventor
Takashi Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69523354D1 publication Critical patent/DE69523354D1/de
Publication of DE69523354T2 publication Critical patent/DE69523354T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
DE69523354T 1994-02-25 1995-02-24 Multiplexer Expired - Lifetime DE69523354T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2859394 1994-02-25

Publications (2)

Publication Number Publication Date
DE69523354D1 true DE69523354D1 (de) 2001-11-29
DE69523354T2 DE69523354T2 (de) 2002-07-11

Family

ID=12252899

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69523354T Expired - Lifetime DE69523354T2 (de) 1994-02-25 1995-02-24 Multiplexer

Country Status (6)

Country Link
US (2) US5701095A (de)
EP (1) EP0669620B1 (de)
KR (1) KR0153850B1 (de)
CN (1) CN1042067C (de)
DE (1) DE69523354T2 (de)
TW (1) TW432795B (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5914906A (en) * 1995-12-20 1999-06-22 International Business Machines Corporation Field programmable memory array
US6480548B1 (en) 1997-11-17 2002-11-12 Silicon Graphics, Inc. Spacial derivative bus encoder and decoder
US6775339B1 (en) 1999-08-27 2004-08-10 Silicon Graphics, Inc. Circuit design for high-speed digital communication
US7031420B1 (en) 1999-12-30 2006-04-18 Silicon Graphics, Inc. System and method for adaptively deskewing parallel data signals relative to a clock
US6417713B1 (en) 1999-12-30 2002-07-09 Silicon Graphics, Inc. Programmable differential delay circuit with fine delay adjustment
US6345005B2 (en) * 2000-01-27 2002-02-05 Mitsubishi Denki Kabushiki Kaisha Integrated circuit with efficient testing arrangement
KR100422593B1 (ko) * 2001-05-03 2004-03-12 주식회사 하이닉스반도체 디코딩 장치 및 방법과 이를 사용한 저항열디지털/아날로그 컨버팅 장치 및 방법
DE10324049B4 (de) * 2003-05-27 2006-10-26 Infineon Technologies Ag Integrierte Schaltung und Verfahren zum Betreiben der integrierten Schaltung
WO2005034607A2 (en) * 2003-10-10 2005-04-21 Atmel Corporation Reduced voltage pre-charge multiplexer
CN100353455C (zh) * 2004-05-26 2007-12-05 钰创科技股份有限公司 具有全速数据变迁架构的半导体集成电路及其设计方法
US7212062B2 (en) * 2005-02-10 2007-05-01 International Business Machines Corporation Power supply noise insensitive multiplexer
US20060176096A1 (en) * 2005-02-10 2006-08-10 International Business Machines Corporation Power supply insensitive delay element
US7355435B2 (en) * 2005-02-10 2008-04-08 International Business Machines Corporation On-chip detection of power supply vulnerabilities
US7471135B2 (en) * 2006-12-05 2008-12-30 Cypress Semiconductor Corp. Multiplexer circuit
US7649395B2 (en) * 2007-05-15 2010-01-19 Ati Technologies Ulc Scan flip-flop with internal latency for scan input
US7821866B1 (en) 2007-11-14 2010-10-26 Cypress Semiconductor Corporation Low impedance column multiplexer circuit and method
KR20090108182A (ko) * 2008-04-11 2009-10-15 삼성전자주식회사 반도체 메모리 장치의 병렬비트 테스트 회로
JP6266328B2 (ja) * 2013-12-12 2018-01-24 ザインエレクトロニクス株式会社 信号多重化装置
US9721624B2 (en) * 2014-12-23 2017-08-01 Arm Limited Memory with multiple write ports
US9947406B2 (en) 2015-02-23 2018-04-17 Qualcomm Incorporated Dynamic tag compare circuits employing P-type field-effect transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and related systems and methods
US10163490B2 (en) 2015-02-23 2018-12-25 Qualcomm Incorporated P-type field-effect transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells, and related memory systems and methods
US9741452B2 (en) 2015-02-23 2017-08-22 Qualcomm Incorporated Read-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) read port(s), and related memory systems and methods
US10026456B2 (en) 2015-02-23 2018-07-17 Qualcomm Incorporated Bitline positive boost write-assist circuits for memory bit cells employing a P-type Field-Effect transistor (PFET) write port(s), and related systems and methods
US10068636B2 (en) * 2016-12-30 2018-09-04 Intel Corporation Apparatuses and methods for accessing and scheduling between a plurality of row buffers
US10680856B1 (en) * 2018-12-06 2020-06-09 Credo Technology Group Limited Thermometer-encoded unrolled DFE selection element
CN112671389B (zh) * 2019-10-15 2024-07-05 瑞昱半导体股份有限公司 多任务器装置与讯号切换方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4280212A (en) * 1979-08-15 1981-07-21 Solid State Scientific, Inc. Multiplexing system for a solid state timing device
JPS6055458A (ja) * 1983-09-05 1985-03-30 Matsushita Electric Ind Co Ltd Ｃｍｏｓトランジスタ回路
JPS60242594A (ja) * 1984-05-16 1985-12-02 Hitachi Micro Comput Eng Ltd 半導体記憶装置
US4888739A (en) * 1988-06-15 1989-12-19 Cypress Semiconductor Corporation First-in first-out buffer memory with improved status flags
US4882709A (en) * 1988-08-25 1989-11-21 Integrated Device Technology, Inc. Conditional write RAM
US5012126A (en) * 1990-06-04 1991-04-30 Motorola, Inc. High speed CMOS multiplexer having reduced propagation delay
US5262990A (en) * 1991-07-12 1993-11-16 Intel Corporation Memory device having selectable number of output pins
GB2267614B (en) * 1992-06-02 1996-01-24 Plessey Semiconductors Ltd Logic cell
DE69329788T2 (de) * 1992-10-14 2001-08-02 Sun Microsystems, Inc. Direktzugriffspeicherentwurf
JP3293935B2 (ja) * 1993-03-12 2002-06-17 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
US5502683A (en) * 1993-04-20 1996-03-26 International Business Machines Corporation Dual ported memory with word line access control
US5497347A (en) * 1994-06-21 1996-03-05 Motorola Inc. BICMOS cache TAG comparator having redundancy and separate read an compare paths
US5506810A (en) * 1994-08-16 1996-04-09 Cirrus Logic, Inc. Dual bank memory and systems using the same

Also Published As

Publication number Publication date
EP0669620B1 (de) 2001-10-24
DE69523354T2 (de) 2002-07-11
EP0669620A3 (de) 1995-12-27
CN1042067C (zh) 1999-02-10
TW432795B (en) 2001-05-01
US5870340A (en) 1999-02-09
KR0153850B1 (ko) 1998-12-01
EP0669620A2 (de) 1995-08-30
CN1113038A (zh) 1995-12-06
KR950025989A (ko) 1995-09-18
US5701095A (en) 1997-12-23

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Legal Events

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