DE69432014T2 - Mehrphasiges mehrfachzugriff-pipelinespeichersystem - Google Patents

Mehrphasiges mehrfachzugriff-pipelinespeichersystem

Info

Publication number
DE69432014T2
DE69432014T2 DE69432014T DE69432014T DE69432014T2 DE 69432014 T2 DE69432014 T2 DE 69432014T2 DE 69432014 T DE69432014 T DE 69432014T DE 69432014 T DE69432014 T DE 69432014T DE 69432014 T2 DE69432014 T2 DE 69432014T2
Authority
DE
Germany
Prior art keywords
storage system
multiple access
access pipeline
phase multiple
pipeline storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69432014T
Other languages
English (en)
Other versions
DE69432014D1 (de
Inventor
Douglas Garde
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Analog Devices Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Publication of DE69432014D1 publication Critical patent/DE69432014D1/de
Application granted granted Critical
Publication of DE69432014T2 publication Critical patent/DE69432014T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69432014T 1993-04-22 1994-04-22 Mehrphasiges mehrfachzugriff-pipelinespeichersystem Expired - Lifetime DE69432014T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/052,073 US5471607A (en) 1993-04-22 1993-04-22 Multi-phase multi-access pipeline memory system
PCT/US1994/004455 WO1994024628A1 (en) 1993-04-22 1994-04-22 Multi-phase multi-access pipeline memory system

Publications (2)

Publication Number Publication Date
DE69432014D1 DE69432014D1 (de) 2003-02-20
DE69432014T2 true DE69432014T2 (de) 2003-11-20

Family

ID=21975282

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69432014T Expired - Lifetime DE69432014T2 (de) 1993-04-22 1994-04-22 Mehrphasiges mehrfachzugriff-pipelinespeichersystem

Country Status (5)

Country Link
US (1) US5471607A (de)
EP (1) EP0695444B1 (de)
JP (1) JPH08509082A (de)
DE (1) DE69432014T2 (de)
WO (1) WO1994024628A1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3579461B2 (ja) 1993-10-15 2004-10-20 株式会社ルネサステクノロジ データ処理システム及びデータ処理装置
US5761466A (en) * 1994-05-09 1998-06-02 Lsi Logic Corporation Soft programmable single-cycle/pipelined micro-programmed control system
JPH0816530A (ja) * 1994-07-04 1996-01-19 Kurieiteibu Design:Kk コプロセサシステムおよび補助演算機能付外部メモリ装置
JP3013714B2 (ja) * 1994-09-28 2000-02-28 日本電気株式会社 半導体記憶装置
JP2970434B2 (ja) * 1994-10-31 1999-11-02 日本電気株式会社 同期型半導体記憶装置およびセンス制御方法
US5954811A (en) * 1996-01-25 1999-09-21 Analog Devices, Inc. Digital signal processor architecture
US5896543A (en) * 1996-01-25 1999-04-20 Analog Devices, Inc. Digital signal processor architecture
GB2310738B (en) * 1996-02-29 2000-02-16 Advanced Risc Mach Ltd Dynamic logic pipeline control
JP2959482B2 (ja) * 1996-08-19 1999-10-06 日本電気株式会社 大規模集積回路
US5790838A (en) * 1996-08-20 1998-08-04 International Business Machines Corporation Pipelined memory interface and method for using the same
US6343352B1 (en) 1997-10-10 2002-01-29 Rambus Inc. Method and apparatus for two step memory write operations
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6263448B1 (en) 1997-10-10 2001-07-17 Rambus Inc. Power control system for synchronous memory device
EP1327991A3 (de) * 1997-10-10 2005-05-11 Rambus Inc. Vorrichtung und Verfahren für Pipeline-Speicheroperationen
AU9693398A (en) 1997-10-10 1999-05-03 Rambus Incorporated Apparatus and method for pipelined memory operations
US6002882A (en) * 1997-11-03 1999-12-14 Analog Devices, Inc. Bidirectional communication port for digital signal processor
US6061779A (en) * 1998-01-16 2000-05-09 Analog Devices, Inc. Digital signal processor having data alignment buffer for performing unaligned data accesses
EP1031988A1 (de) * 1999-02-26 2000-08-30 Texas Instruments Incorporated Verfahren und Vorrichtung zum Zugriff auf einen Speicherkern
US6629223B2 (en) 1998-10-06 2003-09-30 Texas Instruments Incorporated Method and apparatus for accessing a memory core multiple times in a single clock cycle
US7126874B2 (en) * 2004-08-31 2006-10-24 Micron Technology, Inc. Memory system and method for strobing data, command and address signals

Family Cites Families (24)

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Publication number Priority date Publication date Assignee Title
US3896418A (en) * 1971-08-31 1975-07-22 Texas Instruments Inc Synchronous multi-processor system utilizing a single external memory unit
US4050058A (en) * 1973-12-26 1977-09-20 Xerox Corporation Microprocessor with parallel operation
JPS6046461B2 (ja) * 1979-11-26 1985-10-16 株式会社日立製作所 アクセス要求選択回路
US4392200A (en) * 1980-01-28 1983-07-05 Digital Equipment Corporation Cached multiprocessor system with pipeline timing
FR2491703B1 (fr) * 1980-10-03 1988-04-29 Thomson Csf Dispositif de compression et dispositif de decompression temporelle de donnees et systeme de transmission comportant au moins l'un de ces dispositifs
US4866604A (en) * 1981-10-01 1989-09-12 Stratus Computer, Inc. Digital data processing apparatus with pipelined memory cycles
US4547845A (en) * 1982-04-21 1985-10-15 The United States Of America As Represented By The Secretary Of The Navy Split-BUS multiprocessor system
JPS6068461A (ja) * 1983-09-21 1985-04-19 Nec Corp メモリ多重アクセス装置
DE3334797A1 (de) * 1983-09-26 1985-01-03 Siemens AG, 1000 Berlin und 8000 München Multiprozessor-rechner, insbesondere multiprozessor-zentralsteuereinheit eines fernsprech-vermittlungssystems
GB8401807D0 (en) * 1984-01-24 1984-02-29 Int Computers Ltd Pipelined data processing apparatus
US4621362A (en) * 1984-06-04 1986-11-04 International Business Machines Corp. Routing architecture for a multi-ring local area network
US4685088A (en) * 1985-04-15 1987-08-04 International Business Machines Corporation High performance memory system utilizing pipelining techniques
US4817006A (en) * 1986-03-28 1989-03-28 Thomas Engineering, Inc. Pharmaceutical tablet press control mechanism
US5010476A (en) * 1986-06-20 1991-04-23 International Business Machines Corporation Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units
JPS63155340A (ja) * 1986-12-19 1988-06-28 Fujitsu Ltd 記憶装置の読出し方式
JPS6421786A (en) * 1987-07-15 1989-01-25 Nec Corp Semiconductor memory
JPS6443894A (en) * 1987-08-10 1989-02-16 Nec Corp Semiconductor memory
EP0303751B1 (de) * 1987-08-20 1992-05-20 International Business Machines Corporation Schnittstellenmechanismus für Informationsübertragungssteuerung zwischen zwei Vorrichtungen
JP2557077B2 (ja) * 1987-12-21 1996-11-27 エイ・ティ・アンド・ティ グローバル インフォメーション ソルーションズ インターナショナル インコーポレイテッド 同期アクセス方式のキヤラクタ表示システム
US5206833A (en) * 1988-09-12 1993-04-27 Acer Incorporated Pipelined dual port RAM
US5220201A (en) * 1990-06-26 1993-06-15 Canon Kabushiki Kaisha Phase-locked signal generator
JP2765245B2 (ja) * 1991-02-07 1998-06-11 日本電気株式会社 シリアルクロック発生回路
JPH04262450A (ja) * 1991-02-15 1992-09-17 Omron Corp プロセッサ
JP2776098B2 (ja) * 1991-11-27 1998-07-16 松下電器産業株式会社 クロック再生回路および時間軸誤差補正装置

Also Published As

Publication number Publication date
DE69432014D1 (de) 2003-02-20
EP0695444B1 (de) 2003-01-15
US5471607A (en) 1995-11-28
WO1994024628A1 (en) 1994-10-27
EP0695444A4 (de) 2001-09-12
JPH08509082A (ja) 1996-09-24
EP0695444A1 (de) 1996-02-07

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Legal Events

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