DE69426701D1 - Verfahren zum kombinieren von mehreren unabhängig arbeitenden schaltungen in einer einzelpackung - Google Patents

Verfahren zum kombinieren von mehreren unabhängig arbeitenden schaltungen in einer einzelpackung

Info

Publication number
DE69426701D1
DE69426701D1 DE69426701T DE69426701T DE69426701D1 DE 69426701 D1 DE69426701 D1 DE 69426701D1 DE 69426701 T DE69426701 T DE 69426701T DE 69426701 T DE69426701 T DE 69426701T DE 69426701 D1 DE69426701 D1 DE 69426701D1
Authority
DE
Germany
Prior art keywords
combining several
several working
single pack
working circuits
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69426701T
Other languages
English (en)
Other versions
DE69426701T2 (de
Inventor
W Olson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wang Laboratories Inc
Original Assignee
Wang Laboratories Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wang Laboratories Inc filed Critical Wang Laboratories Inc
Publication of DE69426701D1 publication Critical patent/DE69426701D1/de
Application granted granted Critical
Publication of DE69426701T2 publication Critical patent/DE69426701T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE69426701T 1993-10-12 1994-03-24 Verfahren zum kombinieren von mehreren unabhängig arbeitenden schaltungen in einer einzelpackung Expired - Fee Related DE69426701T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/134,809 US5495422A (en) 1993-10-12 1993-10-12 Method for combining a plurality of independently operating circuits within a single package
PCT/US1994/003098 WO1995010854A1 (en) 1993-10-12 1994-03-24 Method for combining a plurality of independently operating circuits within a single package

Publications (2)

Publication Number Publication Date
DE69426701D1 true DE69426701D1 (de) 2001-03-22
DE69426701T2 DE69426701T2 (de) 2001-09-20

Family

ID=22465120

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69426701T Expired - Fee Related DE69426701T2 (de) 1993-10-12 1994-03-24 Verfahren zum kombinieren von mehreren unabhängig arbeitenden schaltungen in einer einzelpackung

Country Status (6)

Country Link
US (1) US5495422A (de)
EP (1) EP0723705B1 (de)
AU (1) AU682357B2 (de)
CA (1) CA2172812C (de)
DE (1) DE69426701T2 (de)
WO (1) WO1995010854A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872448A (en) * 1991-06-18 1999-02-16 Lightspeed Semiconductor Corporation Integrated circuit architecture having an array of test cells providing full controlability for automatic circuit verification
US5615126A (en) * 1994-08-24 1997-03-25 Lsi Logic Corporation High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing
US5596765A (en) * 1994-10-19 1997-01-21 Advanced Micro Devices, Inc. Integrated processor including a device for multiplexing external pin signals
DE69522633T2 (de) * 1994-10-19 2002-07-04 Advanced Micro Devices, Inc. Integrierte Prozessorsysteme für tragbare Informationsgeräte
JP2002516636A (ja) * 1995-12-01 2002-06-04 エルエスアイ ロジック コーポレイション 集積ネットワークブラウザチップ、ネットワークブラウザシステムおよびネットワークデータ通信方法
JP3714969B2 (ja) 1998-03-02 2005-11-09 レクサー・メディア・インコーポレイテッド 改良されたオペレーティングモード検出機能を備えたフラッシュメモリーカード及びユーザフレンドリなインターフェーシングシステム
US6182162B1 (en) 1998-03-02 2001-01-30 Lexar Media, Inc. Externally coupled compact flash memory card that configures itself one of a plurality of appropriate operating protocol modes of a host computer
US6057705A (en) * 1998-05-28 2000-05-02 Microchip Technology Incorporated Programmable pin designation for semiconductor devices
US6279065B1 (en) * 1998-06-03 2001-08-21 Compaq Computer Corporation Computer system with improved memory access
US6901457B1 (en) 1998-11-04 2005-05-31 Sandisk Corporation Multiple mode communications system
EP1212835B1 (de) 1999-09-15 2007-04-25 Thomson Licensing Multi-takt ic mit taktgenerator mit bidirektionneller taktanschlussanordnung
US6648826B2 (en) * 2002-02-01 2003-11-18 Sonosite, Inc. CW beam former in an ASIC
JP4707191B2 (ja) * 2006-09-26 2011-06-22 富士通株式会社 検証支援プログラム、該プログラムを記録した記録媒体、検証支援装置、および検証支援方法
US20100211453A1 (en) * 2007-07-26 2010-08-19 Huang Evan S Method and apparatus for business info provider-based advertising in a local search market

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB168299A (en) * 1921-07-13 1922-06-29 Rohm Ges Improvements in or relating to chucks for drilling machines
JPS5961944A (ja) * 1982-09-30 1984-04-09 Fujitsu Ltd マスタスライス集積回路の製造方法
JPS62293821A (ja) * 1986-06-12 1987-12-21 Nec Corp 論理集積回路
US4864381A (en) * 1986-06-23 1989-09-05 Harris Corporation Hierarchical variable die size gate array architecture
US4922441A (en) * 1987-01-19 1990-05-01 Ricoh Company, Ltd. Gate array device having a memory cell/interconnection region
US5068603A (en) * 1987-10-07 1991-11-26 Xilinx, Inc. Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays
DE3742655A1 (de) * 1987-12-16 1989-07-06 Asea Brown Boveri Verfahren zur herstellung eines anwendungs-spezifischen-integrierten-schaltkreises (asic)
US5369595A (en) * 1988-03-18 1994-11-29 International Business Machines Corporation Method of combining gate array and standard cell circuits on a common semiconductor chip
EP0340901A3 (de) * 1988-03-23 1992-12-30 Du Pont Pixel Systems Limited Zugriffsystem für Speicher mit doppelter Anschlussstelle
DE68929518T2 (de) * 1988-10-05 2005-06-09 Quickturn Design Systems, Inc., Mountain View Verfahren zur Verwendung einer elektronisch wiederkonfigurierbaren Gatterfeld-Logik und dadurch hergestelltes Gerät
JP2891709B2 (ja) * 1989-01-16 1999-05-17 株式会社日立製作所 半導体集積回路装置
JPH02219254A (ja) * 1989-02-20 1990-08-31 Hitachi Ltd 半導体集積回路装置
US5220213A (en) * 1991-03-06 1993-06-15 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5317698A (en) * 1992-08-18 1994-05-31 Actel Corporation FPGA architecture including direct logic function circuit to I/O interconnections

Also Published As

Publication number Publication date
WO1995010854A1 (en) 1995-04-20
CA2172812A1 (en) 1995-04-20
CA2172812C (en) 2006-05-16
EP0723705A1 (de) 1996-07-31
US5495422A (en) 1996-02-27
AU6589994A (en) 1995-05-04
EP0723705B1 (de) 2001-02-14
AU682357B2 (en) 1997-10-02
DE69426701T2 (de) 2001-09-20

Similar Documents

Publication Publication Date Title
DE69826283D1 (de) Verfahren zum bewahren von elementen in einer datenbank
DE69428518D1 (de) Verfahren zum unterscheiden von hämatopoietischen fortpflanzungszellen
DE59704729D1 (de) Verfahren zum betrieb einer speicherzellenanordnung
DE59302742D1 (de) Verfahren zum Betrieb einer Kombianlage
DE59309015D1 (de) Verfahren zum Betreiben einer Frankiermaschine
DE69315137D1 (de) Verfahren zum steuern von mehreren robotern
DE59712859D1 (de) Verfahren zum Instantiieren einer versionsbehafteten Klasse
DE69426701D1 (de) Verfahren zum kombinieren von mehreren unabhängig arbeitenden schaltungen in einer einzelpackung
DE69404182D1 (de) Verfahren zum Betreiben einer Kühlanlage
DE69132009D1 (de) Verfahren zum ziehen von einkristallen
DE69316969D1 (de) Verfahren zum Betrieb einer Kälteanlage
DE69301060D1 (de) Verfahren zum Aufbringen von Lot
DE69425497D1 (de) Verfahren zum anreichern von löslichen ballaststoffen
DE59404620D1 (de) Verfahren zum betreiben einer falzmaschine
DE59706277D1 (de) Verfahren zum Betreiben einer Werkzeugmaschine
DE69412464D1 (de) Verfahren zum bearbeiten von polyolefinen bei hohen schergeschwindigkeiten
ATA104688A (de) Verfahren zum biegen eines werkstueckes
DE59402609D1 (de) Verfahren zum verschliessen von druckmittel führenden kanälen in einem gehäuse
DE59401632D1 (de) Vorrichtung zum Schneiden von Endlos-Papier sowie ein Verfahren zu ihrem Betrieb
DE69306782D1 (de) Verfahren zum verbinden von perfluorelastomeren
DE69518422D1 (de) Verfahren zum manipulieren eines verbindungselementes in der schifffahrt
DE69319347D1 (de) Verfahren zum verkleben von oberflächen
DE59501663D1 (de) Verfahren zum verschweissen von werkstücken
ATA147592A (de) Einrichtung zum beschicken von werkzeugmaschinen
DE69326920D1 (de) Verfahren zum prüfen von artikeln

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee