DE69425306D1 - Verfahren zur Herstellung von Halbleitervorrichtungen mit Schichten von dotierten WSi2 enthaltenden Elektroden - Google Patents

Verfahren zur Herstellung von Halbleitervorrichtungen mit Schichten von dotierten WSi2 enthaltenden Elektroden

Info

Publication number
DE69425306D1
DE69425306D1 DE69425306T DE69425306T DE69425306D1 DE 69425306 D1 DE69425306 D1 DE 69425306D1 DE 69425306 T DE69425306 T DE 69425306T DE 69425306 T DE69425306 T DE 69425306T DE 69425306 D1 DE69425306 D1 DE 69425306D1
Authority
DE
Germany
Prior art keywords
wsi2
layers
semiconductor devices
producing semiconductor
electrodes containing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69425306T
Other languages
English (en)
Inventor
Chen-Hua Douglas Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69425306D1 publication Critical patent/DE69425306D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
DE69425306T 1993-10-04 1994-09-21 Verfahren zur Herstellung von Halbleitervorrichtungen mit Schichten von dotierten WSi2 enthaltenden Elektroden Expired - Lifetime DE69425306D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/131,508 US5395799A (en) 1993-10-04 1993-10-04 Method of fabricating semiconductor devices having electrodes comprising layers of doped tungsten disilicide

Publications (1)

Publication Number Publication Date
DE69425306D1 true DE69425306D1 (de) 2000-08-24

Family

ID=22449756

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69425306T Expired - Lifetime DE69425306D1 (de) 1993-10-04 1994-09-21 Verfahren zur Herstellung von Halbleitervorrichtungen mit Schichten von dotierten WSi2 enthaltenden Elektroden

Country Status (6)

Country Link
US (1) US5395799A (de)
EP (1) EP0646957B1 (de)
JP (1) JP2948486B2 (de)
KR (1) KR0163800B1 (de)
DE (1) DE69425306D1 (de)
TW (1) TW235370B (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5434096A (en) * 1994-10-05 1995-07-18 Taiwan Semiconductor Manufacturing Company Ltd. Method to prevent silicide bubble in the VLSI process
JPH08264660A (ja) * 1995-03-24 1996-10-11 Nec Corp 半導体装置の製造方法
US5840607A (en) * 1996-10-11 1998-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming undoped/in-situ doped/undoped polysilicon sandwich for floating gate application
US6579784B1 (en) 1999-10-18 2003-06-17 Taiwan Semiconductor Manufacturing Company Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers
US7081411B2 (en) * 2003-10-18 2006-07-25 Northrop Grumman Corporation Wafer etching techniques

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816425A (en) * 1981-11-19 1989-03-28 Texas Instruments Incorporated Polycide process for integrated circuits
US4613885A (en) * 1982-02-01 1986-09-23 Texas Instruments Incorporated High-voltage CMOS process
US4443930A (en) * 1982-11-30 1984-04-24 Ncr Corporation Manufacturing method of silicide gates and interconnects for integrated circuits
US4740479A (en) * 1985-07-05 1988-04-26 Siemens Aktiengesellschaft Method for the manufacture of cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories
US4755478A (en) * 1987-08-13 1988-07-05 International Business Machines Corporation Method of forming metal-strapped polysilicon gate electrode for FET device
KR900008868B1 (ko) * 1987-09-30 1990-12-11 삼성전자 주식회사 저항성 접촉을 갖는 반도체 장치의 제조방법
US4859278A (en) * 1988-08-11 1989-08-22 Xerox Corporation Fabrication of high resistive loads utilizing a single level polycide process
KR940003589B1 (ko) * 1991-02-25 1994-04-25 삼성전자 주식회사 BiCMOS 소자의 제조 방법
US5086017A (en) * 1991-03-21 1992-02-04 Industrial Technology Research Institute Self aligned silicide process for gate/runner without extra masking
US5278096A (en) * 1991-12-23 1994-01-11 At&T Bell Laboratories Transistor fabrication method

Also Published As

Publication number Publication date
KR0163800B1 (ko) 1999-02-01
EP0646957B1 (de) 2000-07-19
US5395799A (en) 1995-03-07
EP0646957A1 (de) 1995-04-05
KR950012603A (ko) 1995-05-16
JP2948486B2 (ja) 1999-09-13
TW235370B (en) 1994-12-01
JPH07169712A (ja) 1995-07-04

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Legal Events

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