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1999-06-10 |
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Mehrprozessorsystem mit Zellenvermittlung zur Topologie-invarianten, nachrichtenorientierten Kommunikation
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1997-12-19 |
2001-05-08 |
Storage Technology Corporation |
Method and system for arbitrating path contention in a crossbar interconnect network
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1998-03-27 |
2000-10-24 |
Nexabit Networks Llc |
Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access
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1998-05-13 |
2000-05-16 |
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Method and system for sending frames around a head of line blocked frame in a connection fabric environment
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2000-05-01 |
2006-09-12 |
Industrial Technology Research Institute |
Switching by multistage interconnection of concentrators
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2000-06-16 |
2003-07-08 |
Shuo-Yen Robert Li |
Running-sum adder networks determined by recursive construction of multi-stage networks
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2000-06-22 |
2003-04-29 |
International Business Machines Corporation |
Scalable crossbar switch
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2001-06-15 |
2009-10-27 |
Industrial Technology Research Institute |
Optimizing switching element for minimal latency
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2001-06-15 |
2006-09-05 |
Industrial Technology Research Institute |
Scalable 2-stage interconnections
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2002-11-05 |
2009-06-16 |
Trading Technologies International, Inc. |
System and method for determining implied market information
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2003-12-18 |
2006-08-29 |
Emc Corporation |
Data storage system having port disable mechanism
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2005-03-18 |
2010-04-21 |
富士通株式会社 |
クロスバー装置、制御方法及びプログラム
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2005-09-07 |
2012-03-27 |
Sony Corporation |
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2006-02-22 |
2011-08-02 |
Marvell Israel (M.I.S.L) Ltd. |
Scalable memory architecture for high speed crossbars using variable cell or packet length
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2007-09-13 |
2010-07-07 |
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集積装置およびそのレイアウト方法、並びにプログラム
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2009-03-23 |
2013-06-25 |
Lsi Corporation |
High speed packet FIFO output buffers for switch fabric with speedup
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2009-04-27 |
2014-12-09 |
Lsi Corporation |
Thread synchronization in a multi-thread network communications processor architecture
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2009-04-27 |
2016-09-13 |
Intel Corporation |
Dynamic configuration of processing modules in a network communications processor architecture
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2010-05-18 |
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Intel Corporation |
Early cache eviction in a multi-flow network processor architecture
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2010-03-12 |
2013-07-30 |
Lsi Corporation |
Memory manager for a network communications processor architecture
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2009-04-27 |
2015-11-10 |
Intel Corporation |
Data caching in a network communications processor architecture
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2010-05-18 |
2013-11-05 |
Lsi Corporation |
Root scheduling algorithm in a network processor
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2010-05-18 |
2014-01-28 |
Lsi Corporation |
Packet draining from a scheduling hierarchy in a traffic manager of a network processor
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2010-05-18 |
2014-10-21 |
Lsi Corporation |
Packet draining from a scheduling hierarchy in a traffic manager of a network processor
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2010-05-18 |
2014-03-18 |
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Memory manager for a network communications processor architecture
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2009-04-27 |
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2010-05-18 |
2013-10-22 |
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Multithreaded, superscalar scheduling in a traffic manager of a network processor
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Instruction breakpoints in a multi-core, multi-thread network communications processor architecture
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2010-03-12 |
2013-09-17 |
Lsi Corporation |
Hash processing in a network communications processor architecture
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2010-05-18 |
2014-04-22 |
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Multicast address learning in an input/output adapter of a network processor
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2010-05-18 |
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Agere Systems Llc |
Packet scheduling with guaranteed minimum rate in a traffic manager of a network processor
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2010-05-18 |
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Speculative task reading in a traffic manager of a network processor
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2010-05-18 |
2013-12-31 |
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Byte-accurate scheduling in a network processor
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2009-04-27 |
2015-01-27 |
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Packet assembly module for multi-core, multi-thread network processors
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2009-04-27 |
2015-12-22 |
Intel Corporation |
Data caching in a network communications processor architecture
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2010-05-18 |
2013-08-20 |
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Concurrent linked-list traversal for real-time hash processing in multi-core, multi-thread network processors
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Exception detection and thread rescheduling in a multi-core, multi-thread network processor
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2009-04-27 |
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Thread synchronization in a multi-thread network communications processor architecture
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2010-05-18 |
2014-09-23 |
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Hybrid address mutex mechanism for memory accesses in a network processor
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2009-04-27 |
2015-02-03 |
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Changing a flow identifier of a packet in a multi-thread, multi-flow network processor
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2010-05-18 |
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2010-05-18 |
2014-10-21 |
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Packet assembly module for multi-core, multi-thread network processors
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2009-04-27 |
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Lsi Corporation |
Multicasting traffic manager in a network communications processor architecture
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Hash processing in a network communications processor architecture
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2009-04-27 |
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Sharing of internal pipeline resources of a network processor with external devices
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Reducing data read latency in a network communications processor architecture
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2009-04-27 |
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Task queuing in a multi-flow network processor architecture
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Thread synchronization in a multi-thread, multi-flow network communications processor architecture
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Address learning and aging for network bridging in a network processor
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Processor bus bridge for network processors or the like
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Configurable memory encryption with constant pipeline delay in a multi-core processor
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Modularized scheduling engine for traffic management in a network processor
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2010-05-18 |
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Scheduling hierarchy in a traffic manager of a network processor
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2010-05-18 |
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Network switch with external buffering via looparound path
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2010-05-18 |
2017-09-05 |
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Hierarchical self-organizing classification processing in a network switch
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Allocation of memory buffers based on preferred memory performance
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Packet reassembly processing
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2015-06-26 |
2018-01-16 |
Intel Corporation |
Hardware processors and methods for tightly-coupled heterogeneous computing
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