DE69324992T2 - Datenverarbeitungssystem und -verfahren zur Berechnung der Summe von Basis und Versatz - Google Patents

Datenverarbeitungssystem und -verfahren zur Berechnung der Summe von Basis und Versatz

Info

Publication number
DE69324992T2
DE69324992T2 DE69324992T DE69324992T DE69324992T2 DE 69324992 T2 DE69324992 T2 DE 69324992T2 DE 69324992 T DE69324992 T DE 69324992T DE 69324992 T DE69324992 T DE 69324992T DE 69324992 T2 DE69324992 T2 DE 69324992T2
Authority
DE
Germany
Prior art keywords
offset
sum
calculating
base
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69324992T
Other languages
English (en)
Other versions
DE69324992D1 (de
Inventor
James M Sibigtroth
J Greg Viot
John A Langan
James L Broseghini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69324992D1 publication Critical patent/DE69324992D1/de
Application granted granted Critical
Publication of DE69324992T2 publication Critical patent/DE69324992T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
DE69324992T 1992-10-27 1993-08-26 Datenverarbeitungssystem und -verfahren zur Berechnung der Summe von Basis und Versatz Expired - Fee Related DE69324992T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/967,295 US5386534A (en) 1992-10-27 1992-10-27 Data processing system for generating symmetrical range of addresses of instructing-address-value with the use of inverting sign value

Publications (2)

Publication Number Publication Date
DE69324992D1 DE69324992D1 (de) 1999-06-24
DE69324992T2 true DE69324992T2 (de) 1999-11-11

Family

ID=25512589

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69324992T Expired - Fee Related DE69324992T2 (de) 1992-10-27 1993-08-26 Datenverarbeitungssystem und -verfahren zur Berechnung der Summe von Basis und Versatz

Country Status (5)

Country Link
US (1) US5386534A (de)
EP (1) EP0594969B1 (de)
JP (1) JP3556252B2 (de)
KR (1) KR100285142B1 (de)
DE (1) DE69324992T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512958A (en) * 1994-04-29 1996-04-30 Matsushita Electric Corporation Of America System for controlling the effects of noise in television receivers
US5784534A (en) * 1995-03-31 1998-07-21 Motorola, Inc. Circuit and method for representing fuzzy rule weights during a fuzzy logic operation
JPH0934866A (ja) * 1995-07-18 1997-02-07 Nec Corp マイクロコンピュータ
US5819056A (en) * 1995-10-06 1998-10-06 Advanced Micro Devices, Inc. Instruction buffer organization method and system
KR100290869B1 (ko) * 1998-01-14 2001-06-01 구자홍 복조기의주파수오프셋부호판별장치
KR100574929B1 (ko) * 1999-12-29 2006-05-02 삼성전자주식회사 허미션 대칭 데이터를 위한 주소 발생기
GB2375625B (en) * 2001-05-18 2005-08-31 At & T Lab Cambridge Ltd Microprocessors with improved power efficiency
GB2402757B (en) 2003-06-11 2005-11-02 Advanced Risc Mach Ltd Address offset generation within a data processing system
GB2488980B (en) * 2011-03-07 2020-02-19 Advanced Risc Mach Ltd Address generation in a data processing apparatus

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4025771A (en) * 1974-03-25 1977-05-24 Hughes Aircraft Company Pipe line high speed signal processor
JPS5734251A (en) * 1980-08-07 1982-02-24 Toshiba Corp Address conversion and generating system
US4432053A (en) * 1981-06-29 1984-02-14 Burroughs Corporation Address generating apparatus and method
US4538223A (en) * 1982-09-29 1985-08-27 Microdata Corporation Computer operand address computation
US4531200A (en) * 1982-12-02 1985-07-23 International Business Machines Corporation Indexed-indirect addressing using prefix codes
JPS6015746A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd デ−タ処理装置
JPS62145326A (ja) * 1985-12-20 1987-06-29 Toshiba Corp マイクロプログラム制御回路
US4935867A (en) * 1986-03-04 1990-06-19 Advanced Micro Devices, Inc. Signal processor memory management unit with indirect addressing using selectable offsets and modulo values for indexed address calculations
US5226129A (en) * 1986-10-30 1993-07-06 Nec Corporation Program counter and indirect address calculation system which concurrently performs updating of a program counter and generation of an effective address
US4819165A (en) * 1987-03-27 1989-04-04 Tandem Computers Incorporated System for performing group relative addressing
US5276819A (en) * 1987-05-01 1994-01-04 Hewlett-Packard Company Horizontal computer having register multiconnect for operand address generation during execution of iterations of a loop of program code
JPH01204138A (ja) * 1988-02-09 1989-08-16 Nec Corp 演算回路
US5155818A (en) * 1988-09-28 1992-10-13 Data General Corporation Unconditional wide branch instruction acceleration
US5150471A (en) * 1989-04-20 1992-09-22 Ncr Corporation Method and apparatus for offset register address accessing
US5204953A (en) * 1989-08-04 1993-04-20 Intel Corporation One clock address pipelining in segmentation unit
US5148538A (en) * 1989-10-20 1992-09-15 International Business Machines Corporation Translation look ahead based cache access
JPH03180933A (ja) * 1989-12-08 1991-08-06 Matsushita Electric Ind Co Ltd スタックメモリ
US5283874A (en) * 1991-10-21 1994-02-01 Intel Corporation Cross coupling mechanisms for simultaneously completing consecutive pipeline instructions even if they begin to process at the same microprocessor of the issue fee

Also Published As

Publication number Publication date
JP3556252B2 (ja) 2004-08-18
EP0594969A1 (de) 1994-05-04
EP0594969B1 (de) 1999-05-19
US5386534A (en) 1995-01-31
JPH06222982A (ja) 1994-08-12
DE69324992D1 (de) 1999-06-24
KR940009819A (ko) 1994-05-24
KR100285142B1 (ko) 2001-03-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: SCHUMACHER & WILLSAU, PATENTANWALTSSOZIETAET, 80335 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8339 Ceased/non-payment of the annual fee