DE69304378T2 - Verfahren und Vorrichtung zur Regelung einer Verzögerung über mehrere Verzögerungsbereiche - Google Patents

Verfahren und Vorrichtung zur Regelung einer Verzögerung über mehrere Verzögerungsbereiche

Info

Publication number
DE69304378T2
DE69304378T2 DE69304378T DE69304378T DE69304378T2 DE 69304378 T2 DE69304378 T2 DE 69304378T2 DE 69304378 T DE69304378 T DE 69304378T DE 69304378 T DE69304378 T DE 69304378T DE 69304378 T2 DE69304378 T2 DE 69304378T2
Authority
DE
Germany
Prior art keywords
delay
regulating
over several
ranges
delay over
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69304378T
Other languages
English (en)
Other versions
DE69304378D1 (de
Inventor
Roland Marbot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull Sa Les Clayes Sous Bois Fr
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Application granted granted Critical
Publication of DE69304378D1 publication Critical patent/DE69304378D1/de
Publication of DE69304378T2 publication Critical patent/DE69304378T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
DE69304378T 1992-03-24 1993-03-12 Verfahren und Vorrichtung zur Regelung einer Verzögerung über mehrere Verzögerungsbereiche Expired - Lifetime DE69304378T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9203526A FR2689339B1 (fr) 1992-03-24 1992-03-24 Procede et dispositif de reglage de retard a plusieurs gammes.

Publications (2)

Publication Number Publication Date
DE69304378D1 DE69304378D1 (de) 1996-10-10
DE69304378T2 true DE69304378T2 (de) 1997-01-16

Family

ID=9428010

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69304378T Expired - Lifetime DE69304378T2 (de) 1992-03-24 1993-03-12 Verfahren und Vorrichtung zur Regelung einer Verzögerung über mehrere Verzögerungsbereiche

Country Status (5)

Country Link
US (1) US5521540A (de)
EP (1) EP0562904B1 (de)
JP (1) JP2572706B2 (de)
DE (1) DE69304378T2 (de)
FR (1) FR2689339B1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5589789A (en) * 1993-10-16 1996-12-31 Nec Corporation Bus driver circuit for high-speed data transmission
JP2788022B2 (ja) 1995-02-14 1998-08-20 株式会社日立製作所 光記録媒体
US7092349B2 (en) 1995-02-14 2006-08-15 Hitachi, Ltd. Optical reproducing method optical medium with aligned prepit portion
US5982738A (en) 1995-02-14 1999-11-09 Hitachi, Ltd. Optical recording medium having at least wobbled synchronous information shared between tracks
JP3141762B2 (ja) * 1995-12-13 2001-03-05 株式会社日立製作所 空気流量計測装置及び空気流量計測方法
US5731725A (en) * 1995-12-15 1998-03-24 Unisys Corporation Precision delay circuit
US5959481A (en) * 1997-02-18 1999-09-28 Rambus Inc. Bus driver circuit including a slew rate indicator circuit having a one shot circuit
FR2767982B1 (fr) * 1997-09-04 2001-11-23 Sgs Thomson Microelectronics Circuit a retard variable
DE69700292T2 (de) * 1997-11-18 1999-10-14 Hewlett Packard Co Veränderbare digitale Verzögerungszelle
JP3119224B2 (ja) * 1997-12-25 2000-12-18 日本電気株式会社 可変位相回路
JP2000244286A (ja) * 1999-02-22 2000-09-08 Mitsubishi Electric Corp 電圧制御発振装置
USRE41831E1 (en) 2000-05-23 2010-10-19 Marvell International Ltd. Class B driver
US7095348B1 (en) 2000-05-23 2006-08-22 Marvell International Ltd. Communication driver
US7312739B1 (en) 2000-05-23 2007-12-25 Marvell International Ltd. Communication driver
US7113121B1 (en) 2000-05-23 2006-09-26 Marvell International Ltd. Communication driver
US6775529B1 (en) 2000-07-31 2004-08-10 Marvell International Ltd. Active resistive summer for a transformer hybrid
US6462688B1 (en) 2000-12-18 2002-10-08 Marvell International, Ltd. Direct drive programmable high speed power digital-to-analog converter
US7194037B1 (en) 2000-05-23 2007-03-20 Marvell International Ltd. Active replica transformer hybrid
US7433665B1 (en) 2000-07-31 2008-10-07 Marvell International Ltd. Apparatus and method for converting single-ended signals to a differential signal, and transceiver employing same
US7606547B1 (en) 2000-07-31 2009-10-20 Marvell International Ltd. Active resistance summer for a transformer hybrid
JP2002290217A (ja) * 2001-03-28 2002-10-04 Fujitsu Ltd 遅延回路、遅延回路を含む半導体集積回路装置、及び遅延方法
DE60139490D1 (de) * 2001-12-20 2009-09-17 Texas Instruments Inc Ausgangstreiber mit gesteuerter Anstiegszeit
US6825707B2 (en) 2003-03-10 2004-11-30 Infineon Technologies Ag Current mode logic (CML) circuit concept for a variable delay element
US7312662B1 (en) 2005-08-09 2007-12-25 Marvell International Ltd. Cascode gain boosting system and method for a transmitter
US7577892B1 (en) 2005-08-25 2009-08-18 Marvell International Ltd High speed iterative decoder

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4820944A (en) * 1983-08-01 1989-04-11 Schlumberger Systems & Services, Inc. Method and apparatus for dynamically controlling the timing of signals in automatic test systems
US4737670A (en) * 1984-11-09 1988-04-12 Lsi Logic Corporation Delay control circuit
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
US4833695A (en) * 1987-09-08 1989-05-23 Tektronix, Inc. Apparatus for skew compensating signals
US4797586A (en) * 1987-11-25 1989-01-10 Tektronix, Inc. Controllable delay circuit
US4862020A (en) * 1988-06-20 1989-08-29 Tektronix, Inc. Electronic delay control circuit having pulse width maintenance
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
JPH0728735Y2 (ja) * 1989-05-15 1995-06-28 株式会社アドバンテスト 遅延発生回路
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
JP3077813B2 (ja) * 1990-05-11 2000-08-21 ソニー株式会社 プログラマブル遅延回路
JP3092829U (ja) * 2002-08-30 2003-04-04 早川工業株式会社 ペアタワシ

Also Published As

Publication number Publication date
FR2689339A1 (fr) 1993-10-01
EP0562904A1 (de) 1993-09-29
EP0562904B1 (de) 1996-09-04
JP2572706B2 (ja) 1997-01-16
JPH0613859A (ja) 1994-01-21
DE69304378D1 (de) 1996-10-10
US5521540A (en) 1996-05-28
FR2689339B1 (fr) 1996-12-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL S.A., LES CLAYES SOUS BOIS, FR