DE69304096D1 - Digitale PLL-Schaltung - Google Patents

Digitale PLL-Schaltung

Info

Publication number
DE69304096D1
DE69304096D1 DE69304096T DE69304096T DE69304096D1 DE 69304096 D1 DE69304096 D1 DE 69304096D1 DE 69304096 T DE69304096 T DE 69304096T DE 69304096 T DE69304096 T DE 69304096T DE 69304096 D1 DE69304096 D1 DE 69304096D1
Authority
DE
Germany
Prior art keywords
pll circuit
digital pll
digital
circuit
pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69304096T
Other languages
English (en)
Other versions
DE69304096T2 (de
Inventor
Yuichiro Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69304096D1 publication Critical patent/DE69304096D1/de
Application granted granted Critical
Publication of DE69304096T2 publication Critical patent/DE69304096T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L2007/047—Speed or phase control by synchronisation signals using special codes as synchronising signal using a sine signal or unmodulated carrier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/007—Detection of the synchronisation error by features other than the received signal transition detection of error based on maximum signal power, e.g. peak value, maximizing autocorrelation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
DE69304096T 1992-02-18 1993-02-03 Digitale PLL-Schaltung Expired - Fee Related DE69304096T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4029844A JP2978621B2 (ja) 1992-02-18 1992-02-18 ディジタルｐｌｌ回路

Publications (2)

Publication Number Publication Date
DE69304096D1 true DE69304096D1 (de) 1996-09-26
DE69304096T2 DE69304096T2 (de) 1997-03-27

Family

ID=12287311

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69304096T Expired - Fee Related DE69304096T2 (de) 1992-02-18 1993-02-03 Digitale PLL-Schaltung

Country Status (4)

Country Link
US (1) US5319321A (de)
EP (1) EP0556643B1 (de)
JP (1) JP2978621B2 (de)
DE (1) DE69304096T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5359631A (en) * 1992-09-30 1994-10-25 Cirrus Logic, Inc. Timing recovery circuit for synchronous waveform sampling
KR0134309B1 (ko) * 1994-03-11 1998-04-23 김광호 디지탈 주파수 자동조절회로
KR100553673B1 (ko) * 1999-02-24 2006-02-24 삼성전자주식회사 전압 제어 발진 회로
KR100694039B1 (ko) * 2000-07-20 2007-03-12 삼성전자주식회사 지터 검출 장치 및 그를 이용한 위상 동기 루프
JP2006025365A (ja) * 2004-07-09 2006-01-26 Matsushita Electric Ind Co Ltd オフセット補償機能付きｄ／ａ変換装置およびｄ／ａ変換装置のオフセット補償方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3840821A (en) * 1967-07-27 1974-10-08 Sperry Rand Corp Phase lock loop with sampling techniques for regenerating clock signal associated with data input signals
US3602834A (en) * 1970-06-18 1971-08-31 Ibm Timing recovery circuits
US4333060A (en) * 1980-07-10 1982-06-01 E-Systems, Inc. Phase locked loop for recovering data bit timing
US4805191A (en) * 1987-11-25 1989-02-14 Motorola, Inc. Modem with improved timing recovery using equalized data
GB8903567D0 (en) * 1989-02-16 1989-04-05 British Telecomm An optical network
US5068628A (en) * 1990-11-13 1991-11-26 Level One Communications, Inc. Digitally controlled timing recovery loop

Also Published As

Publication number Publication date
JPH05235752A (ja) 1993-09-10
US5319321A (en) 1994-06-07
JP2978621B2 (ja) 1999-11-15
EP0556643B1 (de) 1996-08-21
EP0556643A1 (de) 1993-08-25
DE69304096T2 (de) 1997-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee