DE69231910D1 - Herstellungsverfahren von Verbindungen - Google Patents

Herstellungsverfahren von Verbindungen

Info

Publication number
DE69231910D1
DE69231910D1 DE69231910T DE69231910T DE69231910D1 DE 69231910 D1 DE69231910 D1 DE 69231910D1 DE 69231910 T DE69231910 T DE 69231910T DE 69231910 T DE69231910 T DE 69231910T DE 69231910 D1 DE69231910 D1 DE 69231910D1
Authority
DE
Germany
Prior art keywords
connections
manufacturing process
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69231910T
Other languages
English (en)
Other versions
DE69231910T2 (de
Inventor
Shingo Kadomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Application granted granted Critical
Publication of DE69231910D1 publication Critical patent/DE69231910D1/de
Publication of DE69231910T2 publication Critical patent/DE69231910T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/902—Capping layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
DE69231910T 1991-08-29 1992-08-28 Herstellungsverfahren von Verbindungen Expired - Fee Related DE69231910T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP24452391 1991-08-29
JP24645091 1991-09-02
JP14152792A JP3191407B2 (ja) 1991-08-29 1992-06-02 配線形成方法

Publications (2)

Publication Number Publication Date
DE69231910D1 true DE69231910D1 (de) 2001-08-09
DE69231910T2 DE69231910T2 (de) 2002-04-04

Family

ID=27318267

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231910T Expired - Fee Related DE69231910T2 (de) 1991-08-29 1992-08-28 Herstellungsverfahren von Verbindungen

Country Status (4)

Country Link
US (1) US5599742A (de)
EP (1) EP0529656B1 (de)
JP (1) JP3191407B2 (de)
DE (1) DE69231910T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3843459B2 (ja) * 1996-09-26 2006-11-08 トヨタ自動車株式会社 チタン系水素吸蔵合金粉末の製造方法
US6133635A (en) * 1997-06-30 2000-10-17 Philips Electronics North America Corp. Process for making self-aligned conductive via structures
JPH1168095A (ja) * 1997-08-11 1999-03-09 Fujitsu Ltd 半導体装置の製造方法
US6232219B1 (en) * 1998-05-20 2001-05-15 Micron Technology, Inc. Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures
US6319822B1 (en) * 1998-10-01 2001-11-20 Taiwan Semiconductor Manufacturing Company Process for forming an integrated contact or via
US6214739B1 (en) 1999-02-05 2001-04-10 Taiwan Semiconductor Manufacturing Company Method of metal etching with in-situ plasma cleaning
US6350687B1 (en) * 1999-03-18 2002-02-26 Advanced Micro Devices, Inc. Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film
EP1307919A4 (de) * 2000-07-12 2009-04-15 California Inst Of Techn Elektrische passivierung von siliziumhaltigen oberflächen unter verwendung organischer schichten
US6937447B2 (en) 2001-09-19 2005-08-30 Kabushiki Kaisha Toshiba Magnetoresistance effect element, its manufacturing method, magnetic reproducing element and magnetic memory
US6682989B1 (en) * 2002-11-20 2004-01-27 Intel Corporation Plating a conductive material on a dielectric material
JP4727170B2 (ja) * 2004-06-23 2011-07-20 東京エレクトロン株式会社 プラズマ処理方法、および後処理方法
US20060032833A1 (en) * 2004-08-10 2006-02-16 Applied Materials, Inc. Encapsulation of post-etch halogenic residue
US20060102197A1 (en) * 2004-11-16 2006-05-18 Kang-Lie Chiang Post-etch treatment to remove residues
JP2007299880A (ja) * 2006-04-28 2007-11-15 Toshiba Corp 磁気抵抗効果素子，および磁気抵抗効果素子の製造方法
JP5044157B2 (ja) * 2006-07-11 2012-10-10 株式会社東芝 磁気抵抗効果素子，磁気ヘッド，および磁気再生装置
JP2008085220A (ja) * 2006-09-28 2008-04-10 Toshiba Corp 磁気抵抗効果素子、磁気ヘッド、および磁気再生装置
JP5039007B2 (ja) * 2008-09-26 2012-10-03 株式会社東芝 磁気抵抗効果素子の製造方法、磁気抵抗効果素子、磁気ヘッドアセンブリ及び磁気記録再生装置
JP5032429B2 (ja) * 2008-09-26 2012-09-26 株式会社東芝 磁気抵抗効果素子の製造方法、磁気抵抗効果素子、磁気ヘッドアセンブリ及び磁気記録再生装置
JP5039006B2 (ja) 2008-09-26 2012-10-03 株式会社東芝 磁気抵抗効果素子の製造方法、磁気抵抗効果素子、磁気ヘッドアセンブリ及び磁気記録再生装置
JP7222940B2 (ja) * 2019-02-18 2023-02-15 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置
JP2022170130A (ja) * 2021-04-28 2022-11-10 ソニーセミコンダクタソリューションズ株式会社 半導体装置及びエッチング方法
WO2023157395A1 (ja) * 2022-02-18 2023-08-24 ローム株式会社 半導体装置およびその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226176B2 (de) * 1973-08-28 1977-07-12
US4208241A (en) * 1978-07-31 1980-06-17 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
GB2042488A (en) * 1979-02-05 1980-09-24 Energy Conversion Devices Inc Electrical conductor and method of making the same
JPS5922374A (ja) * 1982-07-28 1984-02-04 Matsushita Electric Ind Co Ltd 緑色発光ダイオ−ドの製造方法
DE3411659A1 (de) * 1984-03-29 1985-10-03 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von polyoxazol- und polythiazol-vorstufen
GB2168841B (en) * 1984-12-22 1988-07-20 Stc Plc Semiconductor processing
EP0260906B1 (de) * 1986-09-17 1993-03-10 Fujitsu Limited Verfahren zum Herstellen einer Halbleitervorrichtung und Halbleitervorrichtung
NL8902744A (nl) * 1989-11-07 1991-06-03 Koninkl Philips Electronics Nv Werkwijze voor het aanbrengen van sporen uit aluminium of een aluminiumlegering op een substraat.
US5397432A (en) * 1990-06-27 1995-03-14 Fujitsu Limited Method for producing semiconductor integrated circuits and apparatus used in such method
JP3371143B2 (ja) * 1991-06-03 2003-01-27 ソニー株式会社 ドライエッチング方法
US5314576A (en) * 1992-06-09 1994-05-24 Sony Corporation Dry etching method using (SN)x protective layer

Also Published As

Publication number Publication date
US5599742A (en) 1997-02-04
EP0529656A3 (de) 1994-04-13
DE69231910T2 (de) 2002-04-04
EP0529656B1 (de) 2001-07-04
EP0529656A2 (de) 1993-03-03
JP3191407B2 (ja) 2001-07-23
JPH05160123A (ja) 1993-06-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee