DE69231197T2 - Verfahren und Vorrichtung für eine verbesserte Speicherarchitektur - Google Patents

Verfahren und Vorrichtung für eine verbesserte Speicherarchitektur

Info

Publication number
DE69231197T2
DE69231197T2 DE69231197T DE69231197T DE69231197T2 DE 69231197 T2 DE69231197 T2 DE 69231197T2 DE 69231197 T DE69231197 T DE 69231197T DE 69231197 T DE69231197 T DE 69231197T DE 69231197 T2 DE69231197 T2 DE 69231197T2
Authority
DE
Germany
Prior art keywords
store
processor
memory
load
operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69231197T
Other languages
German (de)
English (en)
Other versions
DE69231197D1 (de
Inventor
Michel Cekleov
Jean-Marc Frailong
Eric Jenson
Michael Powell
Pradeep Sindhu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69231197D1 publication Critical patent/DE69231197D1/de
Application granted granted Critical
Publication of DE69231197T2 publication Critical patent/DE69231197T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
DE69231197T 1991-05-17 1992-04-21 Verfahren und Vorrichtung für eine verbesserte Speicherarchitektur Expired - Fee Related DE69231197T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/702,781 US5265233A (en) 1991-05-17 1991-05-17 Method and apparatus for providing total and partial store ordering for a memory in multi-processor system

Publications (2)

Publication Number Publication Date
DE69231197D1 DE69231197D1 (de) 2000-08-03
DE69231197T2 true DE69231197T2 (de) 2001-03-15

Family

ID=24822571

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231197T Expired - Fee Related DE69231197T2 (de) 1991-05-17 1992-04-21 Verfahren und Vorrichtung für eine verbesserte Speicherarchitektur

Country Status (5)

Country Link
US (1) US5265233A (enExample)
EP (1) EP0514024B1 (enExample)
JP (1) JPH05233421A (enExample)
KR (1) KR100243853B1 (enExample)
DE (1) DE69231197T2 (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398325A (en) * 1992-05-07 1995-03-14 Sun Microsystems, Inc. Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems
US5434993A (en) * 1992-11-09 1995-07-18 Sun Microsystems, Inc. Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories
US6144930A (en) * 1993-06-09 2000-11-07 Compaq Computer Corporation Method for providing a memory model of a memory device for use in simulation
US5506967A (en) * 1993-06-15 1996-04-09 Unisys Corporation Storage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architectures
EP0679990B1 (en) * 1994-04-28 2000-03-01 Hewlett-Packard Company A computer apparatus having a means to force sequential instruction execution
US5745732A (en) * 1994-11-15 1998-04-28 Cherukuri; Ravikrishna V. Computer system including system controller with a write buffer and plural read buffers for decoupled busses
US5699538A (en) * 1994-12-09 1997-12-16 International Business Machines Corporation Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor
US6073211A (en) * 1994-12-13 2000-06-06 International Business Machines Corporation Method and system for memory updates within a multiprocessor data processing system
US5692153A (en) * 1995-03-16 1997-11-25 International Business Machines Corporation Method and system for verifying execution order within a multiprocessor data processing system
US5822553A (en) * 1996-03-13 1998-10-13 Diamond Multimedia Systems, Inc. Multiple parallel digital data stream channel controller architecture
US5797043A (en) * 1996-03-13 1998-08-18 Diamond Multimedia Systems, Inc. System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs
US5778244A (en) * 1996-10-07 1998-07-07 Timeplex, Inc. Digital signal processing unit using digital signal processor array with recirculation
US6748493B1 (en) 1998-11-30 2004-06-08 International Business Machines Corporation Method and apparatus for managing memory operations in a data processing system using a store buffer
US6678810B1 (en) 1999-12-30 2004-01-13 Intel Corporation MFENCE and LFENCE micro-architectural implementation method and system
US7538772B1 (en) * 2000-08-23 2009-05-26 Nintendo Co., Ltd. Graphics processing system with enhanced memory controller
US6678807B2 (en) * 2000-12-21 2004-01-13 Intel Corporation System and method for multiple store buffer forwarding in a system with a restrictive memory model
US20050210204A1 (en) * 2003-01-27 2005-09-22 Fujitsu Limited Memory control device, data cache control device, central processing device, storage device control method, data cache control method, and cache control method
WO2004068361A1 (ja) * 2003-01-27 2004-08-12 Fujitsu Limited 記憶制御装置、データキャッシュ制御装置、中央処理装置、記憶装置制御方法、データキャッシュ制御方法およびキャッシュ制御方法
US7360035B2 (en) * 2004-09-01 2008-04-15 International Business Machines Corporation Atomic read/write support in a multi-module memory configuration
US7941585B2 (en) * 2004-09-10 2011-05-10 Cavium Networks, Inc. Local scratchpad and data caching system
US7606998B2 (en) * 2004-09-10 2009-10-20 Cavium Networks, Inc. Store instruction ordering for multi-core processor
WO2008155827A1 (ja) * 2007-06-20 2008-12-24 Fujitsu Limited キャッシュ制御装置及び制御方法
JP5094822B2 (ja) * 2008-12-04 2012-12-12 韓國電子通信研究院 多重プロセッサを含むメモリアクセス装置
KR101635395B1 (ko) * 2010-03-10 2016-07-01 삼성전자주식회사 멀티포트 데이터 캐시 장치 및 멀티포트 데이터 캐시 장치의 제어 방법
US9052890B2 (en) 2010-09-25 2015-06-09 Intel Corporation Execute at commit state update instructions, apparatus, methods, and systems
US8713259B2 (en) * 2010-11-17 2014-04-29 Advanced Micro Devices, Inc. Method and apparatus for reacquiring lines in a cache
US9361103B2 (en) * 2012-11-02 2016-06-07 Advanced Micro Devices, Inc. Store replay policy
JP6191172B2 (ja) * 2013-03-12 2017-09-06 日本電気株式会社 メモリコントローラ、プロセッサ、演算処理方法、及び、演算命令ライブラリ。
US10345883B2 (en) * 2016-05-31 2019-07-09 Taiwan Semiconductor Manufacturing Co., Ltd. Power estimation
US11914511B2 (en) * 2020-06-22 2024-02-27 Apple Inc. Decoupling atomicity from operation size

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4136386A (en) * 1977-10-06 1979-01-23 International Business Machines Corporation Backing store access coordination in a multi-processor system
JPS621067A (ja) * 1985-02-25 1987-01-07 Hitachi Ltd ベクトル処理装置
JPH0731669B2 (ja) * 1986-04-04 1995-04-10 株式会社日立製作所 ベクトル・プロセツサ
US5023776A (en) * 1988-02-22 1991-06-11 International Business Machines Corp. Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
US5148536A (en) * 1988-07-25 1992-09-15 Digital Equipment Corporation Pipeline having an integral cache which processes cache misses and loads data in parallel
US5043886A (en) * 1988-09-16 1991-08-27 Digital Equipment Corporation Load/store with write-intent for write-back caches
US4905141A (en) * 1988-10-25 1990-02-27 International Business Machines Corporation Partitioned cache memory with partition look-aside table (PLAT) for early partition assignment identification
US5202972A (en) * 1988-12-29 1993-04-13 International Business Machines Corporation Store buffer apparatus in a multiprocessor system
US5201041A (en) * 1988-12-29 1993-04-06 International Business Machines Corporation Cache bypass apparatus
US5185871A (en) * 1989-12-26 1993-02-09 International Business Machines Corporation Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions

Also Published As

Publication number Publication date
EP0514024A2 (en) 1992-11-19
US5265233A (en) 1993-11-23
KR920022101A (ko) 1992-12-19
KR100243853B1 (ko) 2000-02-01
EP0514024B1 (en) 2000-06-28
DE69231197D1 (de) 2000-08-03
JPH05233421A (ja) 1993-09-10
EP0514024A3 (enExample) 1994-05-04

Similar Documents

Publication Publication Date Title
DE69231197T2 (de) Verfahren und Vorrichtung für eine verbesserte Speicherarchitektur
DE68924306T2 (de) Mehrprozessorrechneranordnungen mit gemeinsamem Speicher und privaten Cache-Speichern.
DE68927172T2 (de) Multiprozessorsystem mit cache-speichern
DE68922326T2 (de) Speicherwarteschlange für eine festgekoppelte Mehrprozessorenkonfiguration mit einem zweistufigen Cache-Pufferspeicher.
DE68928513T2 (de) Verfahren zur Vorverarbeitung mehrerer Befehle
DE68929224T2 (de) Pipeline, die einen Cachespeicher für Rechnerprozessoren enthält
DE69323790T2 (de) Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem
DE68928677T2 (de) Verfahren und digitaler Computer zur Vorverarbeitung mehrerer Befehle
DE112007003801B3 (de) Vorrichtung mit einer speichereinheit und einer logik zur bereitstellung eines effizienten mechanismus‘ für transaktionalspeicherausführungen in out-of-order-prozessoren
DE3486161T2 (de) Datenverarbeitungssystem mit Datenkohärenz.
DE69027253T2 (de) Multiprozessor-Cachespeichersystem
DE69327288T2 (de) Verfahren und System zur Aufrechterhaltung der Adressenübersetzungspufferspeicher-Kohärenz eines Multiprozessorsystems
DE3587439T2 (de) Gemeinsam benutzter Mehrprozessor-Pipeline-Cachespeicher.
DE69715328T2 (de) System und Verfahren zur Parallelisierung der Durchführung von Speichertransaktionen mittels mehreren Speichermodellen
DE69514165T2 (de) Mehrstufige Cache-Speicheranordnung
DE10085373B4 (de) Verfahren zum Flushen von Cache-Zeilen
DE69127726T2 (de) Kombinierte Warteschlange für Entwertungen und Rücklaufdaten in einem Multiprozessorsystem
DE69506623T2 (de) Datenprozessor mit einer Ausführungseinheit zur Durchführung von Ladebefehlen und Verfahren zu seinem Betrieb
DE3856451T2 (de) Multiprozessor-Digitaldatenverarbeitungssystem
DE3151745C2 (enExample)
DE69729917T2 (de) Cachespeicherräumungsvorrichtung und hiermit versehenes Rechnersystem
DE4218003C2 (de) Cache-Steuereinrichtung für ein sekundäres Cache-Speichersystem
DE3689042T2 (de) Gerät zur Pufferung von Schreibanforderungen.
DE69133302T2 (de) Registerabbildung in einem einzigen Taktzyklus
DE69331039T2 (de) Rechnersystem mit einem Vorausholungscachespeicher

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee